X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=d71fc23115760c06fd9e2eef56ab64ba1dc47770;hb=6af04d5a36a47b11dcf10bb629105600aa5a66eb;hp=89027806bf63a0da710114a5bca5225d36dd8b29;hpb=be465111b552c7c2a2262ac49758a30a8bf1b1d5;p=libsigrokdecode.git

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 8902780..d71fc23 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -141,9 +141,6 @@ class Decoder(srd.Decoder):
             # The width of one UART bit in number of samples.
             self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
 
-    def report(self):
-        pass
-
     # Return true if we reached the middle of the desired bit, false otherwise.
     def reached_bit(self, rxtx, bitnum):
         # bitpos is the samplenumber which is in the middle of the
@@ -225,7 +222,8 @@ class Decoder(srd.Decoder):
 
         b, f = self.databyte[rxtx], self.options['format']
         if f == 'ascii':
-            self.putx(rxtx, [rxtx, [chr(b)]])
+            c = chr(b) if chr(b).isprintable() else '[%02X]' % b
+            self.putx(rxtx, [rxtx, [c]])
         elif f == 'dec':
             self.putx(rxtx, [rxtx, [str(b)]])
         elif f == 'hex':