X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fswd%2Fpd.py;h=3414c35f7cf3a17eff4548522f32e5a1fa57d406;hb=07e40f346ac1ed5ca98f636f2dd0ba5a7fe0011e;hp=4e68f2d364072d2d3ad643960f109f2a068ef415;hpb=4afe40462af650a0df1bfb7bd185ee666f2b30f0;p=libsigrokdecode.git

diff --git a/decoders/swd/pd.py b/decoders/swd/pd.py
index 4e68f2d..3414c35 100644
--- a/decoders/swd/pd.py
+++ b/decoders/swd/pd.py
@@ -19,7 +19,7 @@
 ##
 
 import sigrokdecode as srd
-import re, traceback
+import re
 
 '''
 OUTPUT_PYTHON format:
@@ -92,7 +92,7 @@ class Decoder(srd.Decoder):
         ('parity', 'PARITY'),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
         # SWD data/clock state
         self.state = 'UNKNOWN'
         self.oldclk = -1
@@ -143,13 +143,6 @@ class Decoder(srd.Decoder):
         self.putp(ptype, (self.addr, self.data, self.ack))
 
     def decode(self, ss, es, data):
-        try:
-            return self._decode(ss, es, data)
-        except:
-            traceback.print_exc()
-            raise
-
-    def _decode(self, ss, es, data):
         for (self.samplenum, (clk, dio)) in data:
             if clk == self.oldclk:
                 continue # Not a clock edge.
@@ -347,7 +340,7 @@ class Decoder(srd.Decoder):
                 }[self.addr]
         elif self.apdp == 'AP':
             if self.rw == 'R':
-                return 'W AP%x' % self.addr
+                return 'R AP%x' % self.addr
             elif self.rw == 'W':
                 return 'W AP%x' % self.addr