X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspi%2Fspi.py;h=2f10ef44918f6c48c3295dd1dd01fcf16a0a49c4;hb=781ef9450d82a9c7381aef17fb4974a1e49ec2d2;hp=5e5e74ec5c7123d8a022beb0086e04a7e1f17dc8;hpb=4180cba9a51acd32f69f0f8628bb746ea3e12be6;p=libsigrokdecode.git

diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index 5e5e74e..2f10ef4 100644
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -41,7 +41,7 @@ class Decoder(srd.Decoder):
     id = 'spi'
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
-    desc = '...desc...'
+    desc = 'Full-duplex, synchronous, serial bus.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
@@ -73,6 +73,7 @@ class Decoder(srd.Decoder):
         self.bytesreceived = 0
         self.samplenum = -1
         self.cs_was_deasserted_during_data_word = 0
+        self.oldcs = -1
 
     def start(self, metadata):
         self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
@@ -85,6 +86,14 @@ class Decoder(srd.Decoder):
         # TODO: Either MISO or MOSI could be optional. CS# is optional.
         for (self.samplenum, (miso, mosi, sck, cs)) in data:
 
+            if self.oldcs != cs:
+                # Send all CS# pin value changes.
+                self.put(self.samplenum, self.samplenum, self.out_proto,
+                         ['CS-CHANGE', self.oldcs, cs])
+                self.put(self.samplenum, self.samplenum, self.out_ann,
+                         [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]])
+                self.oldcs = cs
+
             # Ignore sample if the clock pin hasn't changed.
             if sck == self.oldsck:
                 continue
@@ -131,7 +140,7 @@ class Decoder(srd.Decoder):
                 continue
 
             self.put(self.start_sample, self.samplenum, self.out_proto,
-                     ['data', self.mosidata, self.misodata])
+                     ['DATA', self.mosidata, self.misodata])
             self.put(self.start_sample, self.samplenum, self.out_ann,
                      [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
                      self.misodata)]])