X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=4a686ddd204a9fbff6b439f37e90db2f9ef14dda;hb=79065c6f7602f1f02399bcf45bb3ef0cb73587ae;hp=25a9f85f9c059b662fefd203f7e364fdd0edfbb2;hpb=1c49e875623918f8893308307f487a1f551daec4;p=libsigrokdecode.git

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index 25a9f85..4a686dd 100644
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -36,10 +36,11 @@ Packet:
    item, and for each of those also their respective start-/endsample numbers.
  - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
    Both data items are Python numbers (0/1), not strings. At the beginning of
-   the decoding a packet is generated with <data1> = -1 and <data2> being the
-   initial state of the CS# pin or -1 if the chip select pin is not supplied.
+   the decoding a packet is generated with <data1> = None and <data2> being the
+   initial state of the CS# pin or None if the chip select pin is not supplied.
 
 Examples:
+ ['CS-CHANGE', None, 1]
  ['CS-CHANGE', 1, 0]
  ['DATA', 0xff, 0x3a]
  ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
@@ -110,6 +111,10 @@ class Decoder(srd.Decoder):
         ('mosi-bits', 'MOSI bits', (3,)),
         ('other', 'Other', (4,)),
     )
+    binary = (
+        ('miso', 'MISO'),
+        ('mosi', 'MOSI'),
+    )
 
     def __init__(self):
         self.samplerate = None
@@ -121,7 +126,7 @@ class Decoder(srd.Decoder):
         self.ss_block = -1
         self.samplenum = -1
         self.cs_was_deasserted = False
-        self.oldcs = -1
+        self.oldcs = None
         self.oldpins = None
         self.have_cs = self.have_miso = self.have_mosi = None
         self.no_cs_notification = False
@@ -133,6 +138,7 @@ class Decoder(srd.Decoder):
     def start(self):
         self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
+        self.out_bin = self.register(srd.OUTPUT_BINARY)
         self.out_bitrate = self.register(srd.OUTPUT_META,
                 meta=(int, 'Bitrate', 'Bitrate during transfers'))
 
@@ -148,8 +154,10 @@ class Decoder(srd.Decoder):
 
         if self.have_miso:
             ss, es = self.misobits[-1][1], self.misobits[0][2]
+            self.put(ss, es, self.out_bin, (0, bytes([so])))
         if self.have_mosi:
             ss, es = self.mosibits[-1][1], self.mosibits[0][2]
+            self.put(ss, es, self.out_bin, (1, bytes([si])))
 
         self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
         self.put(ss, es, self.out_python, ['DATA', si, so])
@@ -175,14 +183,16 @@ class Decoder(srd.Decoder):
         self.mosibits = [] if self.have_mosi else None
         self.bitcount = 0
 
+    def cs_asserted(self, cs):
+        active_low = (self.options['cs_polarity'] == 'active-low')
+        return (cs == 0) if active_low else (cs == 1)
+
     def handle_bit(self, miso, mosi, clk, cs):
         # If this is the first bit of a dataword, save its sample number.
         if self.bitcount == 0:
             self.ss_block = self.samplenum
-            self.cs_was_deasserted = False
-            if self.have_cs:
-                active_low = (self.options['cs_polarity'] == 'active-low')
-                self.cs_was_deasserted = (cs == 1) if active_low else (cs == 0)
+            self.cs_was_deasserted = \
+                not self.cs_asserted(cs) if self.have_cs else False
 
         ws = self.options['wordsize']
 
@@ -246,6 +256,10 @@ class Decoder(srd.Decoder):
             # Reset decoder state when CS# changes (and the CS# pin is used).
             self.reset_decoder_state()
 
+        # We only care about samples if CS# is asserted.
+        if self.have_cs and not self.cs_asserted(cs):
+            return
+
         # Ignore sample if the clock pin hasn't changed.
         if clk == self.oldclk:
             return
@@ -286,7 +300,7 @@ class Decoder(srd.Decoder):
 
             # Tell stacked decoders that we don't have a CS# signal.
             if not self.no_cs_notification and not self.have_cs:
-                self.put(0, 0, self.out_python, ['CS-CHANGE', -1, -1])
+                self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
                 self.no_cs_notification = True
 
             self.find_clk_edge(miso, mosi, clk, cs)