X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspdif%2Fpd.py;h=126a0274b5087a45214dccf504741c74191cca6b;hb=e144452bcdd5f2abbe6b6f3da41ad64f67e39def;hp=e22f654a906f519135867881cfbca2e2a19b5d81;hpb=5e39fa54152db51fd9bdfb33edfd55a54493821d;p=libsigrokdecode.git

diff --git a/decoders/spdif/pd.py b/decoders/spdif/pd.py
index e22f654..126a027 100644
--- a/decoders/spdif/pd.py
+++ b/decoders/spdif/pd.py
@@ -14,8 +14,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -31,24 +30,25 @@ class Decoder(srd.Decoder):
     desc = 'Serial bus for connecting digital audio devices.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['spdif']
+    outputs = []
+    tags = ['Audio', 'PC']
     channels = (
         {'id': 'data', 'name': 'Data', 'desc': 'Data line'},
     )
     annotations = (
         ('bitrate', 'Bitrate / baudrate'),
         ('preamble', 'Preamble'),
-        ('bits', 'Bits'),
-        ('aux', 'Auxillary-audio-databits'),
-        ('samples', 'Audio Samples'),
+        ('bit', 'Bit'),
+        ('aux', 'Auxillary-audio-databit'),
+        ('sample', 'Audio Sample'),
         ('validity', 'Data Valid'),
         ('subcode', 'Subcode data'),
         ('chan_stat', 'Channnel Status'),
         ('parity', 'Parity Bit'),
     )
     annotation_rows = (
-        ('info', 'Info', (0, 1, 3, 5, 6, 7, 8)),
         ('bits', 'Bits', (2,)),
+        ('info', 'Info', (0, 1, 3, 5, 6, 7, 8)),
         ('samples', 'Samples', (4,)),
     )
 
@@ -59,6 +59,9 @@ class Decoder(srd.Decoder):
         self.put(self.ss_edge, self.samplenum, self.out_ann, data)
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.state = 'GET FIRST PULSE WIDTH'
         self.ss_edge = None
         self.first_edge = True
@@ -80,9 +83,6 @@ class Decoder(srd.Decoder):
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
-        # Assume that the initial pin state is logic 0.
-        self.initial_pins = [0]
-
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
             self.samplerate = value