X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fsle44xx%2F__init__.py;h=0eb02856ca1bf29233d0ab64e9a520e7e51c0542;hb=e4f70391abbb153364a534d45a59026961ce1b1f;hp=1bc718996f1f976cdb831cbb78c1b94aaeaf1fa9;hpb=7e87b2f7522312d5dda5231c1de75fb6bbbdf60c;p=libsigrokdecode.git

diff --git a/decoders/sle44xx/__init__.py b/decoders/sle44xx/__init__.py
index 1bc7189..0eb0285 100644
--- a/decoders/sle44xx/__init__.py
+++ b/decoders/sle44xx/__init__.py
@@ -18,8 +18,9 @@
 ##
 
 '''
-SLE 4418/28/32/42 implement a 2-wire protocol (CLK and I/O) for comunication
-along the RST signal which is used to abort unnecessarily long memory reads.
+SLE 4418/28/32/42 memory cards implement a 2-wire protocol (CLK and I/O)
+for data communication, along with the RST signal which resets the card's
+internal state, and can terminate currently executing long memory reads.
 '''
 
 from .pd import Decoder