X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Frtc8564%2Fpd.py;h=bb72fdc1f57a44ab8847d2101835ee42f3305b18;hb=c761524941fcb2237ceb65082e504e5e48e62a05;hp=ce6ef7574ffe7c53401789dd79211e70e5442dcf;hpb=bff3a0a0031a32e19c1170e5a387197d879944ff;p=libsigrokdecode.git

diff --git a/decoders/rtc8564/pd.py b/decoders/rtc8564/pd.py
index ce6ef75..bb72fdc 100644
--- a/decoders/rtc8564/pd.py
+++ b/decoders/rtc8564/pd.py
@@ -24,6 +24,13 @@ import sigrokdecode as srd
 def bcd2int(b):
     return (b & 0x0f) + ((b >> 4) * 10)
 
+def reg_list():
+    l = []
+    for i in range(8 + 1):
+        l.append(('reg-0x%02x' % i, 'Register 0x%02x' % i))
+
+    return tuple(l)
+
 class Decoder(srd.Decoder):
     api_version = 1
     id = 'rtc8564'
@@ -33,31 +40,15 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['i2c']
     outputs = ['rtc8564']
-    probes = []
-    optional_probes = [
-        {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
-        {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
-        {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
-    ]
-    options = {}
-    annotations = [
-        ['reg-0x00', 'Register 0x00'],
-        ['reg-0x01', 'Register 0x01'],
-        ['reg-0x02', 'Register 0x02'],
-        ['reg-0x03', 'Register 0x03'],
-        ['reg-0x04', 'Register 0x04'],
-        ['reg-0x05', 'Register 0x05'],
-        ['reg-0x06', 'Register 0x06'],
-        ['reg-0x07', 'Register 0x07'],
-        ['reg-0x08', 'Register 0x08'],
-        ['read', 'Read date/time'],
-        ['write', 'Write date/time'],
-        ['bit-reserved', 'Reserved bit'],
-        ['bit-vl', 'VL bit'],
-        ['bit-century', 'Century bit'],
-        ['reg-read', 'Register read'],
-        ['reg-write', 'Register write'],
-    ]
+    annotations = reg_list() + (
+        ('read', 'Read date/time'),
+        ('write', 'Write date/time'),
+        ('bit-reserved', 'Reserved bit'),
+        ('bit-vl', 'VL bit'),
+        ('bit-century', 'Century bit'),
+        ('reg-read', 'Register read'),
+        ('reg-write', 'Register write'),
+    )
     annotation_rows = (
         ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
         ('regs', 'Register access', (14, 15)),
@@ -76,7 +67,6 @@ class Decoder(srd.Decoder):
         self.bits = []
 
     def start(self):
-        # self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def putx(self, data):