X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Frgb_led_ws281x%2Fpd.py;h=5f355942b392d3b751115ab76bf345bdf91fe125;hb=5e8090d7d30fb0915fc1b54f3ec098c69a417745;hp=b4f7c581d7e8f14b971fef5a912a56c9c42be64b;hpb=10aeb8ea8b183394cebc0033f048f49f4262b57d;p=libsigrokdecode.git diff --git a/decoders/rgb_led_ws281x/pd.py b/decoders/rgb_led_ws281x/pd.py index b4f7c58..5f35594 100644 --- a/decoders/rgb_led_ws281x/pd.py +++ b/decoders/rgb_led_ws281x/pd.py @@ -18,11 +18,13 @@ ## import sigrokdecode as srd -from functools import reduce +from common.srdhelper import bitpack_msb class SamplerateError(Exception): pass +( ANN_BIT, ANN_RESET, ANN_RGB, ) = range(3) + class Decoder(srd.Decoder): api_version = 3 id = 'rgb_led_ws281x' @@ -31,7 +33,8 @@ class Decoder(srd.Decoder): desc = 'RGB LED string protocol (WS281x).' license = 'gplv3+' inputs = ['logic'] - outputs = ['rgb_led_ws281x'] + outputs = [] + tags = ['Display', 'IC'] channels = ( {'id': 'din', 'name': 'DIN', 'desc': 'DIN data line'}, ) @@ -41,8 +44,12 @@ class Decoder(srd.Decoder): ('rgb', 'RGB'), ) annotation_rows = ( - ('bit', 'Bits', (0, 1)), - ('rgb', 'RGB', (2,)), + ('bits', 'Bits', (ANN_BIT, ANN_RESET,)), + ('rgb-vals', 'RGB values', (ANN_RGB,)), + ) + options = ( + {'id': 'type', 'desc': 'RGB or RGBW', 'default': 'RGB', + 'values': ('RGB', 'RGBW')}, ) def __init__(self): @@ -50,12 +57,7 @@ class Decoder(srd.Decoder): def reset(self): self.samplerate = None - self.oldpin = None - self.ss_packet = None - self.ss = None - self.es = None self.bits = [] - self.inreset = False def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) @@ -64,70 +66,110 @@ class Decoder(srd.Decoder): if key == srd.SRD_CONF_SAMPLERATE: self.samplerate = value - def handle_bits(self, samplenum): - if len(self.bits) == 24: - grb = reduce(lambda a, b: (a << 1) | b, self.bits) + def putg(self, ss, es, cls, text): + self.put(ss, es, self.out_ann, [cls, text]) + + def handle_bits(self): + if len(self.bits) < self.need_bits: + return + grb = bitpack_msb(self.bits, 0) + if self.options['type'] == 'RGB': rgb = (grb & 0xff0000) >> 8 | (grb & 0x00ff00) << 8 | (grb & 0x0000ff) - self.put(self.ss_packet, samplenum, self.out_ann, - [2, ['#%06x' % rgb]]) - self.bits = [] - self.ss_packet = None + text = '#{:06x}'.format(rgb) + else: + rgb = (grb & 0xff0000) >> 8 | (grb & 0x00ff00) << 8 | (grb & 0xff0000ff) + text = '#{:08x}'.format(rgb) + ss_packet, es_packet = self.bits[0][1], self.bits[-1][2] + self.putg(ss_packet, es_packet, ANN_RGB, [text]) + self.bits.clear() + + def handle_bit(self, ss, es, value, ann_late = False): + if not ann_late: + text = ['{:d}'.format(value)] + self.putg(ss, es, ANN_BIT, text) + item = (value, ss, es) + self.bits.append(item) + self.handle_bits() + if ann_late: + text = ['{:d}'.format(value)] + self.putg(ss, es, ANN_BIT, text) def decode(self): if not self.samplerate: raise SamplerateError('Cannot decode without samplerate.') - + self.need_bits = len(self.options['type']) * 8 + + # Either check for edges which communicate bit values, or for + # long periods of idle level which represent a reset pulse. + # Track the left-most, right-most, and inner edge positions of + # a bit. The positive period's width determines the bit's value. + # Initially synchronize to the input stream by searching for a + # low period, which preceeds a data bit or starts a reset pulse. + # Don't annotate the very first reset pulse, but process it. We + # may not see the right-most edge of a data bit when reset is + # adjacent to that bit time. + cond_bit_starts = {0: 'r'} + cond_inbit_edge = {0: 'f'} + samples_625ns = int(self.samplerate * 625e-9) + samples_50us = round(self.samplerate * 50e-6) + cond_reset_pulse = {'skip': samples_50us + 1} + conds = [cond_bit_starts, cond_inbit_edge, cond_reset_pulse] + ss_bit, inv_bit, es_bit = None, None, None + pin, = self.wait({0: 'l'}) + inv_bit = self.samplenum + check_reset = False while True: - # TODO: Come up with more appropriate self.wait() conditions. - (pin,) = self.wait() - - if self.oldpin is None: - self.oldpin = pin - continue - - # Check RESET condition (manufacturer recommends 50 usec minimal, - # but real minimum is ~10 usec). - if not self.inreset and not pin and self.es is not None and \ - (self.samplenum - self.es) / self.samplerate > 50e-6: - - # Decode last bit value. - tH = (self.es - self.ss) / self.samplerate - bit_ = True if tH >= 625e-9 else False - - self.bits.append(bit_) - self.handle_bits(self.es) - - self.put(self.ss, self.es, self.out_ann, [0, ['%d' % bit_]]) - self.put(self.es, self.samplenum, self.out_ann, - [1, ['RESET', 'RST', 'R']]) - - self.inreset = True - self.bits = [] - self.ss_packet = None - self.ss = None - - if not self.oldpin and pin: - # Rising edge. - if self.ss and self.es: - period = self.samplenum - self.ss - duty = self.es - self.ss + pin, = self.wait(conds) + + # Check RESET condition. Manufacturers may disagree on the + # minimal pulse width. 50us are recommended in datasheets, + # experiments suggest the limit is around 10us. + # When the RESET pulse is adjacent to the low phase of the + # last bit time, we have no appropriate condition for the + # bit time's end location. That's why this BIT's annotation + # is shorter (only spans the high phase), and the RESET + # annotation immediately follows (spans from the falling edge + # to the end of the minimum RESET pulse width). + if check_reset and self.matched[2]: + es_bit = inv_bit + ss_rst, es_rst = inv_bit, self.samplenum + + if ss_bit and inv_bit and es_bit: + # Decode last bit value. Use the last processed bit's + # width for comparison when available. Fallback to an + # arbitrary threshold otherwise (which can result in + # false detection of value 1 for those captures where + # high and low pulses are of similar width). + duty = inv_bit - ss_bit + thres = samples_625ns + if self.bits: + period = self.bits[-1][2] - self.bits[-1][1] + thres = period * 0.5 + bit_value = 1 if duty >= thres else 0 + self.handle_bit(ss_bit, inv_bit, bit_value, True) + + if ss_rst and es_rst: + text = ['RESET', 'RST', 'R'] + self.putg(ss_rst, es_rst, ANN_RESET, text) + check_reset = False + + self.bits.clear() + ss_bit, inv_bit, es_bit = None, None, None + + # Rising edge starts a bit time. Falling edge ends its high + # period. Get the previous bit's duty cycle and thus its + # bit value when the next bit starts. + if self.matched[0]: # and pin: + check_reset = False + if ss_bit and inv_bit: + # Got a previous bit? Handle it. + es_bit = self.samplenum + period = es_bit - ss_bit + duty = inv_bit - ss_bit # Ideal duty for T0H: 33%, T1H: 66%. - bit_ = (duty / period) > 0.5 - - self.put(self.ss, self.samplenum, self.out_ann, - [0, ['%d' % bit_]]) - - self.bits.append(bit_) - self.handle_bits(self.samplenum) - - if self.ss_packet is None: - self.ss_packet = self.samplenum - - self.ss = self.samplenum - - elif self.oldpin and not pin: - # Falling edge. - self.inreset = False - self.es = self.samplenum - - self.oldpin = pin + bit_value = 1 if (duty / period) > 0.5 else 0 + self.handle_bit(ss_bit, es_bit, bit_value) + ss_bit, inv_bit, es_bit = self.samplenum, None, None + if self.matched[1]: # and not pin: + check_reset = True + inv_bit = self.samplenum