X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fparallel%2Fpd.py;h=cae269f8d524c5bf403164f8ac0e048ee28edf34;hb=4e4f8527de0927f2eb1d98e90b58e018ba28d341;hp=2de9dde41854c80f06507ceb4273f40d60af20b6;hpb=f2a5df42ea41e6c4370d4efa1a27ab942ba1ddff;p=libsigrokdecode.git

diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py
index 2de9dde..cae269f 100644
--- a/decoders/parallel/pd.py
+++ b/decoders/parallel/pd.py
@@ -18,12 +18,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# Parallel (sync) bus protocol decoder
-
 import sigrokdecode as srd
 
 '''
-Protocol output format:
+OUTPUT_PYTHON format:
 
 Packet:
 [<ptype>, <pdata>]
@@ -57,11 +55,11 @@ Packet:
 '''
 
 def probe_list(num_probes):
-    l = []
+    l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}]
     for i in range(num_probes):
         d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
         l.append(d)
-    return l
+    return tuple(l)
 
 class Decoder(srd.Decoder):
     api_version = 1
@@ -72,20 +70,19 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['parallel']
-    probes = [
-        {'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'},
-    ]
     optional_probes = probe_list(8)
-    options = {
-        'clock_edge': ['Clock edge to sample on', 'rising'],
-        'wordsize': ['Word size of the data', 1],
-        'endianness': ['Endianness of the data', 'little'],
-        'format': ['Data format', 'hex'],
-    }
-    annotations = [
-        ['items', 'Items'],
-        ['words', 'Words'],
-    ]
+    options = (
+        {'id': 'clock_edge', 'desc': 'Clock edge to sample on',
+            'default': 'rising', 'values': ('rising', 'falling')},
+        {'id': 'wordsize', 'desc': 'Word size of the data',
+            'default': 1},
+        {'id': 'endianness', 'desc': 'Endianness of the data',
+            'default': 'little', 'values': ('little', 'big')},
+    )
+    annotations = (
+        ('items', 'Items'),
+        ('words', 'Words'),
+    )
 
     def __init__(self):
         self.oldclk = None
@@ -98,21 +95,18 @@ class Decoder(srd.Decoder):
         self.first = True
         self.state = 'IDLE'
 
-    def start(self, metadata):
-        self.out_proto = self.add(srd.OUTPUT_PYTHON, 'parallel')
-        self.out_ann = self.add(srd.OUTPUT_ANN, 'parallel')
-
-    def report(self):
-        pass
+    def start(self):
+        self.out_python = self.register(srd.OUTPUT_PYTHON)
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def putpb(self, data):
-        self.put(self.ss_item, self.es_item, self.out_proto, data)
+        self.put(self.ss_item, self.es_item, self.out_python, data)
 
     def putb(self, data):
         self.put(self.ss_item, self.es_item, self.out_ann, data)
 
     def putpw(self, data):
-        self.put(self.ss_word, self.es_word, self.out_proto, data)
+        self.put(self.ss_word, self.es_word, self.out_python, data)
 
     def putw(self, data):
         self.put(self.ss_word, self.es_word, self.out_ann, data)
@@ -149,7 +143,7 @@ class Decoder(srd.Decoder):
         if self.itemcount < ws:
             return
 
-        # Output annotations/proto for a word (a collection of items).
+        # Output annotations/python for a word (a collection of items).
         word = 0
         for i in range(ws):
             if endian == 'little':
@@ -190,7 +184,10 @@ class Decoder(srd.Decoder):
 
             # State machine.
             if self.state == 'IDLE':
-                self.find_clk_edge(pins[0], pins[1:])
+                if pins[0] not in (0, 1):
+                    self.handle_bits(pins[1:])
+                else:
+                    self.find_clk_edge(pins[0], pins[1:])
             else:
                 raise Exception('Invalid state: %s' % self.state)