X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fparallel%2Fpd.py;h=593b39b234140b2bfc5f0ff51cceed6bea47b519;hb=6f7dd46d60a7ca2f1893f5a7d5fd7e87212743f7;hp=094b12a3595dff6e2cb83867145827bee22e2901;hpb=6a15597a7b3f901b566b7bfc8c484a14e0fb6a11;p=libsigrokdecode.git diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py index 094b12a..593b39b 100644 --- a/decoders/parallel/pd.py +++ b/decoders/parallel/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2013 Uwe Hermann +## Copyright (C) 2013-2016 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,8 +14,7 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd @@ -61,8 +60,13 @@ def channel_list(num_channels): l.append(d) return tuple(l) +class ChannelError(Exception): + pass + +NUM_CHANNELS = 8 + class Decoder(srd.Decoder): - api_version = 1 + api_version = 3 id = 'parallel' name = 'Parallel' longname = 'Parallel sync bus' @@ -70,7 +74,7 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['parallel'] - optional_channels = channel_list(8) + optional_channels = channel_list(NUM_CHANNELS) options = ( {'id': 'clock_edge', 'desc': 'Clock edge to sample on', 'default': 'rising', 'values': ('rising', 'falling')}, @@ -84,15 +88,14 @@ class Decoder(srd.Decoder): ) def __init__(self): - self.oldclk = None + self.reset() + + def reset(self): self.items = [] - self.itemcount = 0 self.saved_item = None - self.samplenum = 0 - self.oldpins = None self.ss_item = self.es_item = None self.first = True - self.state = 'IDLE' + self.num_channels = 0 def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) @@ -111,19 +114,17 @@ class Decoder(srd.Decoder): self.put(self.ss_word, self.es_word, self.out_ann, data) def handle_bits(self, datapins): - # If this is the first item in a word, save its sample number. - if self.itemcount == 0: - self.ss_word = self.samplenum - # Get the bits for this item. - item, used_pins = 0, datapins.count(b'\x01') + datapins.count(b'\x00') + item, used_pins = 0, datapins.count(1) + datapins.count(0) for i in range(used_pins): item |= datapins[i] << i + # Save the item, and its sample number if it's the first part of a word. + if not self.items: + self.ss_word = self.samplenum self.items.append(item) - self.itemcount += 1 - if self.first == True: + if self.first: # Save the start sample and item for later (no output yet). self.ss_item = self.samplenum self.first = False @@ -136,57 +137,48 @@ class Decoder(srd.Decoder): self.ss_item = self.samplenum self.saved_item = item - endian, ws = self.options['endianness'], self.options['wordsize'] - # Get as many items as the configured wordsize says. - if self.itemcount < ws: + ws = self.options['wordsize'] + if len(self.items) < ws: return # Output annotations/python for a word (a collection of items). + # NOTE that this feature is currently not effective. The emission + # of Python annotations is commented out. + endian = self.options['endianness'] + if endian == 'little': + self.items.reverse() word = 0 for i in range(ws): - if endian == 'little': - word |= self.items[i] << ((ws - 1 - i) * used_pins) - elif endian == 'big': - word |= self.items[i] << (i * used_pins) + word |= self.items[i] << (i * used_pins) self.es_word = self.samplenum # self.putpw(['WORD', word]) # self.putw([1, ['%X' % word]]) self.ss_word = self.samplenum - self.itemcount, self.items = 0, [] - - def find_clk_edge(self, clk, datapins): - # Ignore sample if the clock pin hasn't changed. - if clk == self.oldclk: - return - self.oldclk = clk - - # Sample data on rising/falling clock edge (depends on config). - c = self.options['clock_edge'] - if c == 'rising' and clk == 0: # Sample on rising clock edge. - return - elif c == 'falling' and clk == 1: # Sample on falling clock edge. - return - - # Found the correct clock edge, now get the bits. - self.handle_bits(datapins) - - def decode(self, ss, es, data): - for (self.samplenum, pins) in data: - - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins = pins + self.items = [] - # State machine. - if self.state == 'IDLE': - if pins[0] not in (0, 1): - self.handle_bits(pins[1:]) - else: - self.find_clk_edge(pins[0], pins[1:]) - else: - raise Exception('Invalid state: %s' % self.state) + def decode(self): + for i in range(len(self.optional_channels)): + if self.has_channel(i): + self.num_channels += 1 + + if self.num_channels == 0: + raise ChannelError('At least one channel has to be supplied.') + + if not self.has_channel(0): + # CLK was not supplied, sample on ANY edge of ANY of the pins + # (but only of those pins that were actually supplied). + conds = [] + for i in range(1, len(self.optional_channels)): + if self.has_channel(i): + conds.append({i: 'e'}) + else: + # Sample on the rising or falling CLK edge (depends on config). + edge = self.options['clock_edge'][0] + conds = [{0: edge}] + while True: + pins = self.wait(conds) + self.handle_bits(pins[1:])