X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fparallel%2Fpd.py;h=4c09d86235e45b0d332511f91826ae59c364e191;hb=b0ac80e2f0a147ddaeab525604d8b0cacf0fd6cd;hp=c8ac2b0f74d2211b86f9a3b88c8f031a23e91223;hpb=97b874bd0b6913ed52df1b8aac5e7491479fac9a;p=libsigrokdecode.git

diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py
index c8ac2b0..4c09d86 100644
--- a/decoders/parallel/pd.py
+++ b/decoders/parallel/pd.py
@@ -88,6 +88,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.items = []
         self.itemcount = 0
         self.saved_item = None
@@ -173,10 +176,11 @@ class Decoder(srd.Decoder):
             for i in range(1, len(self.optional_channels)):
                 if self.has_channel(i):
                     conds.append({i: 'e'})
-            while True:
-                self.handle_bits(self.wait(conds)[1:])
         else:
             # Sample on the rising or falling CLK edge (depends on config).
-            while True:
-                pins = self.wait({0: self.options['clock_edge'][0]})
-                self.handle_bits(pins[1:])
+            edge = self.options['clock_edge'][0]
+            conds = [{0: edge}]
+
+        while True:
+            pins = self.wait(conds)
+            self.handle_bits(pins[1:])