X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fltc242x%2Fpd.py;h=27ae5b99a23e82591c12cec78395b7f59b377fb8;hb=42233a55607c17e7b6325dc231c66f35d2edbb22;hp=4999a4d51c0bae1e5b762a8e9c87d4060500aaed;hpb=a3b9585c554843a6db0c8468b2f37598dbe29bac;p=libsigrokdecode.git

diff --git a/decoders/ltc242x/pd.py b/decoders/ltc242x/pd.py
index 4999a4d..27ae5b9 100644
--- a/decoders/ltc242x/pd.py
+++ b/decoders/ltc242x/pd.py
@@ -19,8 +19,7 @@
 
 import sigrokdecode as srd
 
-channel_format = ['Channel %d', 'Ch %d', '%d']
-input_voltage_format = ['%fV', '%fV', '%.6fV', '%.2fV']
+input_voltage_format = ['%.6fV', '%.2fV']
 
 class Decoder(srd.Decoder):
     api_version = 3
@@ -33,15 +32,15 @@ class Decoder(srd.Decoder):
     outputs = []
     tags = ['IC', 'Analog/digital']
     annotations = (
-        ('channel', 'Channel'),
-        ('input', 'Input voltage'),
+        ('ch0_voltage', 'CH0 voltage'),
+        ('ch1_voltage', 'CH1 voltage'),
     )
     annotation_rows = (
-        ('channel', 'Channel', (0,)),
-        ('input', 'Input voltage', (1,)),
+        ('ch0_voltages', 'CH0 voltages', (0,)),
+        ('ch1_voltages', 'CH1 voltages', (1,)),
     )
     options = (
-        {'id': 'ref', 'desc': 'Reference voltage', 'default': 1.5},
+        {'id': 'vref', 'desc': 'Reference voltage (V)', 'default': 1.5},
     )
 
     def __init__(self):
@@ -54,23 +53,16 @@ class Decoder(srd.Decoder):
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
-    def handle_channel(self, data):
-        channel = (data & (1 << 22)) >> 22
-        ann = []
-        for format in channel_format:
-            ann.append(format % channel)
-
-        self.put(self.ss, self.es, self.out_ann, [0, ann])
-
     def handle_input_voltage(self, data):
         input_voltage = data & 0x3FFFFF
         input_voltage = -(2**21 - input_voltage)
-        input_voltage = (input_voltage / 0xfffff) * self.options['ref']
+        input_voltage = (input_voltage / 0xfffff) * self.options['vref']
         ann = []
         for format in input_voltage_format:
             ann.append(format % input_voltage)
 
-        self.put(self.ss, self.es, self.out_ann, [1, ann])
+        channel = (data & (1 << 22)) >> 22
+        self.put(self.ss, self.es, self.out_ann, [channel, ann])
 
     def decode(self, ss, es, data):
         ptype = data[0]
@@ -80,7 +72,6 @@ class Decoder(srd.Decoder):
             if cs_old is not None and cs_old == 0 and cs_new == 1:
                 self.es = es
                 self.data >>= 1
-                self.handle_channel(self.data)
                 self.handle_input_voltage(self.data)
 
                 self.data = 0