X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fjtag%2Fpd.py;h=fec75d65772ba02e9b2b51bcba9fb4c45ffce363;hb=24a3d8d0b9b1c0d543e408261aa85e31032b90d8;hp=ea6887b6023709cbb291c00cb6793fbf3418d693;hpb=4c3b1846c9c307c1c35f86d259ddb968ed92718d;p=libsigrokdecode.git

diff --git a/decoders/jtag/pd.py b/decoders/jtag/pd.py
index ea6887b..fec75d6 100644
--- a/decoders/jtag/pd.py
+++ b/decoders/jtag/pd.py
@@ -18,12 +18,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# JTAG protocol decoder
-
 import sigrokdecode as srd
 
 '''
-Protocol output format:
+OUTPUT_PYTHON format:
 
 JTAG packet:
 [<packet-type>, <data>]
@@ -55,12 +53,6 @@ jtag_states = [
         'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
 ]
 
-def get_annotation_classes():
-    l = []
-    for s in jtag_states:
-        l.append([s.lower(), s])
-    return l
-
 class Decoder(srd.Decoder):
     api_version = 1
     id = 'jtag'
@@ -70,19 +62,18 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['jtag']
-    probes = [
+    probes = (
         {'id': 'tdi',  'name': 'TDI',  'desc': 'Test data input'},
         {'id': 'tdo',  'name': 'TDO',  'desc': 'Test data output'},
         {'id': 'tck',  'name': 'TCK',  'desc': 'Test clock'},
         {'id': 'tms',  'name': 'TMS',  'desc': 'Test mode select'},
-    ]
-    optional_probes = [
+    )
+    optional_probes = (
         {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
         {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
         {'id': 'rtck', 'name': 'RTCK',  'desc': 'Return clock signal'},
-    ]
-    options = {}
-    annotations = get_annotation_classes()
+    )
+    annotations = tuple([tuple([s.lower(), s]) for s in jtag_states])
 
     def __init__(self, **kwargs):
         # self.state = 'TEST-LOGIC-RESET'
@@ -98,14 +89,14 @@ class Decoder(srd.Decoder):
         self.first = True
 
     def start(self):
-        self.out_proto = self.register(srd.OUTPUT_PYTHON)
+        self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def putx(self, data):
         self.put(self.ss_item, self.es_item, self.out_ann, data)
 
     def putp(self, data):
-        self.put(self.ss_item, self.es_item, self.out_proto, data)
+        self.put(self.ss_item, self.es_item, self.out_python, data)
 
     def advance_state_machine(self, tms):
         self.oldstate = self.state