X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fjitter%2Fpd.py;h=220790efc425ced65137902fccc0cbc3d254cd8b;hb=03fe8db14b32a625c4041e3a8890bbf809679544;hp=4fadbcbd23570ab08072030e5fc5c925a4910f93;hpb=54dad54a0215683b594cc891c9e41f79530b7f1d;p=libsigrokdecode.git

diff --git a/decoders/jitter/pd.py b/decoders/jitter/pd.py
index 4fadbcb..220790e 100644
--- a/decoders/jitter/pd.py
+++ b/decoders/jitter/pd.py
@@ -14,8 +14,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -38,7 +37,8 @@ class Decoder(srd.Decoder):
     desc = 'Retrieves the timing jitter between two digital signals.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['jitter']
+    outputs = []
+    tags = ['Clock/timing', 'Util']
     channels = (
         {'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'},
         {'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'},
@@ -51,19 +51,22 @@ class Decoder(srd.Decoder):
     )
     annotations = (
         ('jitter', 'Jitter value'),
-        ('clk_missed', 'Clock missed'),
-        ('sig_missed', 'Signal missed'),
+        ('clk_miss', 'Clock miss'),
+        ('sig_miss', 'Signal miss'),
     )
     annotation_rows = (
-        ('jitter', 'Jitter values', (0,)),
-        ('clk_missed', 'Clock missed', (1,)),
-        ('sig_missed', 'Signal missed', (2,)),
+        ('jitter_vals', 'Jitter values', (0,)),
+        ('clk_misses', 'Clock misses', (1,)),
+        ('sig_misses', 'Signal misses', (2,)),
     )
     binary = (
         ('ascii-float', 'Jitter values as newline-separated ASCII floats'),
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.state = 'CLK'
         self.samplerate = None
         self.oldclk, self.oldsig = 0, 0