X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fir_rc5%2Fpd.py;h=38b479327eaab9c2d6f5e4793faf7ba0c71f9833;hb=66a6eee7b0783f816187e75324df09a729a4070e;hp=cd94eae1159a59d816bb940622017e023e5d3d23;hpb=16211e24f7a34590f02e9f8a327b1eb3647c7c62;p=libsigrokdecode.git

diff --git a/decoders/ir_rc5/pd.py b/decoders/ir_rc5/pd.py
index cd94eae..38b4793 100644
--- a/decoders/ir_rc5/pd.py
+++ b/decoders/ir_rc5/pd.py
@@ -22,7 +22,7 @@ import sigrokdecode as srd
 from .lists import *
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'ir_rc5'
     name = 'IR RC-5'
     longname = 'IR RC-5'
@@ -30,23 +30,24 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['ir_rc5']
-    probes = [
+    channels = (
         {'id': 'ir', 'name': 'IR', 'desc': 'IR data line'},
-    ]
-    optional_probes = []
-    options = {
-        'polarity': ['Polarity', 'active-low'],
-        'protocol': ['Protocol type', 'standard'],
-    }
-    annotations = [
-        ['bit', 'Bit'],
-        ['startbit1', 'Startbit 1'],
-        ['startbit2', 'Startbit 2'],
-        ['togglebit-0', 'Toggle bit 0'],
-        ['togglebit-1', 'Toggle bit 1'],
-        ['address', 'Address'],
-        ['command', 'Command'],
-    ]
+    )
+    options = (
+        {'id': 'polarity', 'desc': 'Polarity', 'default': 'active-low',
+            'values': ('active-low', 'active-high')},
+        {'id': 'protocol', 'desc': 'Protocol type', 'default': 'standard',
+            'values': ('standard', 'extended')},
+    )
+    annotations = (
+        ('bit', 'Bit'),
+        ('startbit1', 'Startbit 1'),
+        ('startbit2', 'Startbit 2'),
+        ('togglebit-0', 'Toggle bit 0'),
+        ('togglebit-1', 'Toggle bit 1'),
+        ('address', 'Address'),
+        ('command', 'Command'),
+    )
     annotation_rows = (
         ('bits', 'Bits', (0,)),
         ('fields', 'Fields', (1, 2, 3, 4, 5, 6)),
@@ -174,7 +175,7 @@ class Decoder(srd.Decoder):
             if bit != None:
                 self.bits.append([self.samplenum, bit])
 
-            if len(self.bits) == 14 + 1:
+            if len(self.bits) == 14:
                 self.handle_bits()
                 self.reset_decoder_state()