X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fdcf77%2Fpd.py;h=acb6bdafce926465b0b3997b11cdccdb9712c5b8;hb=a6ec01439c60e589d7c6f4632f60e26ee317be9f;hp=3a97d827734c71929cf245e6c4c2e7a325ebc8c7;hpb=40935087ca8a2c63fb224228c3f7dcbe74d48d20;p=libsigrokdecode.git

diff --git a/decoders/dcf77/pd.py b/decoders/dcf77/pd.py
index 3a97d82..acb6bda 100644
--- a/decoders/dcf77/pd.py
+++ b/decoders/dcf77/pd.py
@@ -32,13 +32,14 @@ class Decoder(srd.Decoder):
     desc = 'European longwave time signal (77.5kHz carrier signal).'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['dcf77']
+    outputs = []
+    tags = ['Clock/timing']
     channels = (
         {'id': 'data', 'name': 'DATA', 'desc': 'DATA line'},
     )
     annotations = (
         ('start-of-minute', 'Start of minute'),
-        ('special-bits', 'Special bits (civil warnings, weather forecast)'),
+        ('special-bit', 'Special bit (civil warnings, weather forecast)'),
         ('call-bit', 'Call bit'),
         ('summer-time', 'Summer time announcement'),
         ('cest', 'CEST bit'),
@@ -54,9 +55,9 @@ class Decoder(srd.Decoder):
         ('month', 'Month'),
         ('year', 'Year'),
         ('date-parity', 'Date parity bit'),
-        ('raw-bits', 'Raw bits'),
-        ('unknown-bits', 'Unknown bits'),
-        ('warnings', 'Human-readable warnings'),
+        ('raw-bit', 'Raw bit'),
+        ('unknown-bit', 'Unknown bit'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('bits', 'Bits', (17, 18)),
@@ -249,7 +250,8 @@ class Decoder(srd.Decoder):
             self.putx([16, ['Date parity: %s' % s, 'DP: %s' % s]])
             self.datebits = []
         else:
-            raise Exception('Invalid DCF77 bit: %d' % c)
+            self.putx([19, ['Invalid DCF77 bit: %d' % c,
+                            'Invalid bit: %d' % c, 'Inv: %d' % c]])
 
     def decode(self):
         if not self.samplerate:
@@ -298,11 +300,12 @@ class Decoder(srd.Decoder):
                 elif len_high_ms in range(161, 260 + 1):
                     bit = 1
                 else:
-                    bit = -1 # TODO: Error?
+                    bit = -1
 
-                # There's no bit 59, make sure none is decoded.
-                if bit in (0, 1) and self.bitcount in range(0, 58 + 1):
+                if bit in (0, 1):
                     self.handle_dcf77_bit(bit)
                     self.bitcount += 1
+                else:
+                    self.putx([19, ['Invalid bit timing', 'Inv timing', 'Inv']])
 
                 self.state = 'WAIT FOR RISING EDGE'