X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fcjtag%2Fpd.py;h=885ececf636a1cabdf93e9d5a9d88abdcd3807b1;hb=7aab31bb8a46aeaded3ba682cc3ebfc22a70dbcd;hp=a5c398e671a31322502dc9c7d1c9665b3964d15c;hpb=e349cbe9c80b772d5b96c94d24719b2cb49e0c4f;p=libsigrokdecode.git

diff --git a/decoders/cjtag/pd.py b/decoders/cjtag/pd.py
index a5c398e..885ecec 100644
--- a/decoders/cjtag/pd.py
+++ b/decoders/cjtag/pd.py
@@ -89,8 +89,8 @@ class Decoder(srd.Decoder):
         ('bits-tdo', 'Bits (TDO)', (17,)),
         ('bitstrings-tdi', 'Bitstrings (TDI)', (18,)),
         ('bitstrings-tdo', 'Bitstrings (TDO)', (19,)),
-        ('bit-tms', 'Bit (TMS)', (20,)),
-        ('state-tapc', 'TAPC state', (21,)),
+        ('bits-tms', 'Bits (TMS)', (20,)),
+        ('states-tapc', 'TAPC states', (21,)),
         ('states', 'States', tuple(range(15 + 1))),
     )
 
@@ -138,33 +138,33 @@ class Decoder(srd.Decoder):
         self.oldstate = self.state
 
         if self.cjtagstate.startswith('CJTAG-'):
-            self.oacp = self.oacp + 1
-            if (self.oacp > 4 and self.oaclen == 12):
+            self.oacp += 1
+            if self.oacp > 4 and self.oaclen == 12:
                 self.cjtagstate = 'CJTAG-EC'
 
-            if (self.oacp == 8 and tms == 0):
+            if self.oacp == 8 and tms == 0:
                 self.oaclen = 36
-            if (self.oacp > 8 and self.oaclen == 36):
+            if self.oacp > 8 and self.oaclen == 36:
                 self.cjtagstate = 'CJTAG-SPARE'
-            if (self.oacp > 13 and self.oaclen == 36):
+            if self.oacp > 13 and self.oaclen == 36:
                 self.cjtagstate = 'CJTAG-TPDEL'
-            if (self.oacp > 16 and self.oaclen == 36):
+            if self.oacp > 16 and self.oaclen == 36:
                 self.cjtagstate = 'CJTAG-TPREV'
-            if (self.oacp > 18 and self.oaclen == 36):
+            if self.oacp > 18 and self.oaclen == 36:
                 self.cjtagstate = 'CJTAG-TPST'
-            if (self.oacp > 23 and self.oaclen == 36):
+            if self.oacp > 23 and self.oaclen == 36:
                 self.cjtagstate = 'CJTAG-RDYC'
-            if (self.oacp > 25 and self.oaclen == 36):
+            if self.oacp > 25 and self.oaclen == 36:
                 self.cjtagstate = 'CJTAG-DLYC'
-            if (self.oacp > 27 and self.oaclen == 36):
+            if self.oacp > 27 and self.oaclen == 36:
                 self.cjtagstate = 'CJTAG-SCNFMT'
 
-            if (self.oacp > 8 and self.oaclen == 12):
+            if self.oacp > 8 and self.oaclen == 12:
                 self.cjtagstate = 'CJTAG-CP'
-            if (self.oacp > 32 and self.oaclen == 36):
+            if self.oacp > 32 and self.oaclen == 36:
                 self.cjtagstate = 'CJTAG-CP'
 
-            if (self.oacp > self.oaclen):
+            if self.oacp > self.oaclen:
                 self.cjtagstate = 'OSCAN1'
                 self.oscan1cycle = 1
                 # Because Nuclei cJTAG device asserts a reset during cJTAG
@@ -281,7 +281,7 @@ class Decoder(srd.Decoder):
         self.ss_item = self.samplenum
 
     def handle_tms_edge(self, tck, tms):
-        self.escape_edges = self.escape_edges + 1
+        self.escape_edges += 1
 
     def handle_tapc_state(self, tck, tms):
         self.oldcjtagstate = self.cjtagstate
@@ -305,17 +305,14 @@ class Decoder(srd.Decoder):
             (tdi, tdo, tck, tms, trst, srst, rtck) = self.wait({2: 'r'})
             self.handle_tapc_state(tck, tms)
 
-            if (self.cjtagstate == 'OSCAN1'):
-                if (self.oscan1cycle == 0): # nTDI
-                    if (tms == 0):
-                        tdi_real = 1
-                    else:
-                        tdi_real = 0
+            if self.cjtagstate == 'OSCAN1':
+                if self.oscan1cycle == 0: # nTDI
+                    tdi_real = 1 if (tms == 0) else 0
                     self.oscan1cycle = 1
-                elif (self.oscan1cycle == 1): # TMS
+                elif self.oscan1cycle == 1: # TMS
                     tms_real = tms
                     self.oscan1cycle = 2
-                elif (self.oscan1cycle == 2): # TDO
+                elif self.oscan1cycle == 2: # TDO
                     tdo_real = tms
                     self.handle_rising_tck_edge(tdi_real, tdo_real, tck, tms_real, trst, srst, rtck)
                     self.oscan1cycle = 0
@@ -324,6 +321,6 @@ class Decoder(srd.Decoder):
 
             while (tck == 1):
                 (tdi, tdo, tck, tms_n, trst, srst, rtck) = self.wait([{2: 'f'}, {3: 'e'}])
-                if (tms_n != tms):
+                if tms_n != tms:
                     tms = tms_n
                     self.handle_tms_edge(tck, tms)