X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fadxl345%2Fpd.py;h=2d53e4c0d17bf249658098feddecd918404243af;hb=a9e9573999e59154192a73dda0e9ad36868d6fbe;hp=5b47c0be6c64bcde6f934a41609526070d416d55;hpb=f47d3a2dfc223156c32b935a6241e136d70d4a70;p=libsigrokdecode.git diff --git a/decoders/adxl345/pd.py b/decoders/adxl345/pd.py index 5b47c0b..2d53e4c 100644 --- a/decoders/adxl345/pd.py +++ b/decoders/adxl345/pd.py @@ -18,17 +18,16 @@ ## import sigrokdecode as srd +from common.srdhelper import SrdIntEnum from .lists import * WORD_SIZE = 8 class Channel(): - MISO = 0 - MOSI = 1 + MISO, MOSI = range(2) class Operation(): - READ = 0 - WRITE = 1 + READ, WRITE = range(2) class BitType(): ENABLE = {1: ['Enable %s', 'En %s', '%s '], 0: ['Disable %s', 'Dis %s', '!%s '],} @@ -59,6 +58,10 @@ class Bit(): annotation[index] = str(annotation[index] % self.name) return annotation +Ann = SrdIntEnum.from_str('Ann', 'READ WRITE MB REG_ADDRESS REG_DATA WARNING') + +St = SrdIntEnum.from_str('St', 'IDLE ADDRESS_BYTE DATA') + class Decoder(srd.Decoder): api_version = 3 id = 'adxl345' @@ -78,23 +81,21 @@ class Decoder(srd.Decoder): ('warning', 'Warning'), ) annotation_rows = ( - ('reg', 'Registers', (0, 1, 2, 3)), - ('data', 'Data', (4, 5)), + ('reg', 'Registers', (Ann.READ, Ann.WRITE, Ann.MB, Ann.REG_ADDRESS)), + ('data', 'Data', (Ann.REG_DATA, Ann.WARNING)), ) def __init__(self): self.reset() def reset(self): - self.mosi = [] - self.miso = [] + self.mosi, self.miso = [], [] self.reg = [] self.operation = None self.address = 0 self.data = -1 - self.state = 'IDLE' - self.ss = -1 - self.es = -1 + self.state = St.IDLE + self.ss, self.es = -1, -1 self.samples_per_bit = 0 def start(self): @@ -108,23 +109,21 @@ class Decoder(srd.Decoder): self.put(start, start + self.samples_per_bit, self.out_ann, data) def putbs(self, data, start_index, stop_index): + start_index = self.reverse_bit_index(start_index, WORD_SIZE) + stop_index = self.reverse_bit_index(stop_index, WORD_SIZE) start = self.ss + (self.samples_per_bit * start_index) stop = start + (self.samples_per_bit * (stop_index - start_index + 1)) self.put(start, stop, self.out_ann, data) def handle_reg_with_scaling_factor(self, data, factor, name, unit, error_msg): if data == 0 and error_msg is not None: - self.putx([5, error_msg]) + self.putx([Ann.WARNING, error_msg]) else: result = (data * factor) / 1000 - ann = ['%s: %f %s' % (name, result, unit), '%f %s' % (result, unit)] - self.putx([4, ann]) + self.putx([Ann.REG_DATA, ['%s: %f %s' % (name, result, unit), '%f %s' % (result, unit)]]) def handle_reg_bit_msg(self, bit, index, en_msg, dis_msg): - if bit: - self.putb([4, [en_msg]], index) - else: - self.putb([4, [dis_msg]], index) + self.putb([Ann.REG_DATA, [en_msg if bit else dis_msg]], index) def interpret_bits(self, data, bits): bits_values = [] @@ -136,8 +135,7 @@ class Decoder(srd.Decoder): continue bit = bits[index] bit.set_value(bits_values[index]) - bit_annotation = bit.get_bit_annotation() - self.putb([4, bit_annotation], index) + self.putb([Ann.REG_DATA, bit.get_bit_annotation()], index) return list(reversed(bits_values)) @@ -157,42 +155,41 @@ class Decoder(srd.Decoder): data <<= 8 self.data |= data self.put(self.start_index, self.es, self.out_ann, - [4, ['%s: 0x%04X' % (axis, self.data), str(data)]]) + [Ann.REG_DATA, ['%s: 0x%04X' % (axis, self.data), str(data)]]) self.data = -1 else: - self.putx([4, [str(data)]]) + self.putx([Ann.REG_DATA, [str(data)]]) - def handle_reg_0x1D(self, data): + def handle_reg_0x1d(self, data): self.handle_reg_with_scaling_factor(data, 62.5, 'Threshold', 'g', error_messages['undesirable']) - def handle_reg_0x1E(self, data): + def handle_reg_0x1e(self, data): self.handle_reg_with_scaling_factor(data, 15.6, 'OFSX', 'g', None) - def handle_reg_0x1F(self, data): + def handle_reg_0x1f(self, data): self.handle_reg_with_scaling_factor(data, 15.6, 'OFSY', 'g', None) def handle_reg_0x20(self, data): self.handle_reg_with_scaling_factor(data, 15.6, 'OFSZ', 'g', None) def handle_reg_0x21(self, data): - self.handle_reg_with_scaling_factor(data, 0.625, 'Time', 's', + self.handle_reg_with_scaling_factor(data, 0.625, 'Duration', 's', error_messages['dis_single_double']) def handle_reg_0x22(self, data): - self.handle_reg_with_scaling_factor(data, 62.5, 'Latent', 's', + self.handle_reg_with_scaling_factor(data, 1.25, 'Latency', 's', error_messages['dis_double']) def handle_reg_0x23(self, data): - self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's', + self.handle_reg_with_scaling_factor(data, 1.25, 'Window', 's', error_messages['dis_double']) def handle_reg_0x24(self, data): - self.handle_reg_with_scaling_factor(data, 62.5, 'Latent', 's', - error_messages['undesirable']) + self.handle_reg_0x1d(data) def handle_reg_0x25(self, data): - self.handle_reg_0x1D(data) + self.handle_reg_0x1d(data) def handle_reg_0x26(self, data): self.handle_reg_with_scaling_factor(data, 1000, 'Time', 's', @@ -210,13 +207,13 @@ class Decoder(srd.Decoder): self.interpret_bits(data, bits) def handle_reg_0x28(self, data): - self.handle_reg_0x1D(data) + self.handle_reg_0x1d(data) def handle_reg_0x29(self, data): self.handle_reg_with_scaling_factor(data, 5, 'Time', 's', error_messages['undesirable']) - def handle_reg_0x2A(self, data): + def handle_reg_0x2a(self, data): bits = [Bit('', BitType.UNUSED), Bit('', BitType.UNUSED), Bit('', BitType.UNUSED), @@ -228,7 +225,7 @@ class Decoder(srd.Decoder): Bit('TAP_Z', BitType.ENABLE)] self.interpret_bits(data, bits) - def handle_reg_0x2B(self, data): + def handle_reg_0x2b(self, data): bits = [Bit('', BitType.UNUSED), Bit('ACT_X', BitType.SOURCE), Bit('ACT_Y', BitType.SOURCE), @@ -240,21 +237,18 @@ class Decoder(srd.Decoder): Bit('TAP_Z', BitType.SOURCE)] self.interpret_bits(data, bits) - def handle_reg_0x2C(self, data): + def handle_reg_0x2c(self, data): bits = [Bit('', BitType.UNUSED), Bit('', BitType.UNUSED), Bit('', BitType.UNUSED), Bit('', BitType.OTHER, {1: ['Reduce power', 'Reduce pw', 'Red pw'], 0: ['Normal operation', 'Normal op', 'Norm op'],})] bits_values = self.interpret_bits(data, bits) - start_index = 0 - stop_index = 3 - rate = self.get_decimal_number(bits_values, start_index, start_index) - self.putbs([4, ['%f' % rate_code[rate]]], - self.reverse_bit_index(stop_index, WORD_SIZE), - self.reverse_bit_index(start_index, WORD_SIZE)) + start_index, stop_index = 0, 3 + rate = self.get_decimal_number(bits_values, start_index, stop_index) + self.putbs([Ann.REG_DATA, ['%f' % rate_code[rate]]], stop_index, start_index) - def handle_reg_0x2D(self, data): + def handle_reg_0x2d(self, data): bits = [Bit('', BitType.UNUSED), Bit('', BitType.UNUSED), Bit('', BitType.OTHER, {1: ['Link'], 0: ['Unlink'], }), @@ -263,15 +257,12 @@ class Decoder(srd.Decoder): Bit('', BitType.OTHER, {1: ['Sleep mode', 'Sleep', 'Slp'], 0: ['Normal mode', 'Normal', 'Nrm'],})] bits_values = self.interpret_bits(data, bits) - start_index = 0 - stop_index = 1 + start_index, stop_index = 0, 1 wakeup = self.get_decimal_number(bits_values, start_index, stop_index) frequency = 2 ** (~wakeup & 0x03) - self.putbs([4, ['%d Hz' % frequency]], - self.reverse_bit_index(stop_index, WORD_SIZE), - self.reverse_bit_index(start_index, WORD_SIZE)) + self.putbs([Ann.REG_DATA, ['%d Hz' % frequency]], stop_index, start_index) - def handle_reg_0x2E(self, data): + def handle_reg_0x2e(self, data): bits = [Bit('DATA_READY', BitType.ENABLE), Bit('SINGLE_TAP', BitType.ENABLE), Bit('DOUBLE_TAP', BitType.ENABLE), @@ -282,7 +273,7 @@ class Decoder(srd.Decoder): Bit('Overrun', BitType.ENABLE)] self.interpret_bits(data, bits) - def handle_reg_0x2F(self, data): + def handle_reg_0x2f(self, data): bits = [Bit('DATA_READY', BitType.INTERRUPT), Bit('SINGLE_TAP', BitType.INTERRUPT), Bit('DOUBLE_TAP', BitType.INTERRUPT), @@ -313,17 +304,14 @@ class Decoder(srd.Decoder): Bit('', BitType.OTHER, {1: ['MSB mode', 'MSB'], 0: ['LSB mode', 'LSB'],})] bits_values = self.interpret_bits(data, bits) - start_index = 0 - stop_index = 1 + start_index, stop_index = 0, 1 range_g = self.get_decimal_number(bits_values, start_index, stop_index) result = 2 ** (range_g + 1) - self.putbs([4, ['+/-%d g' % result]], - self.reverse_bit_index(stop_index, WORD_SIZE), - self.reverse_bit_index(start_index, WORD_SIZE)) + self.putbs([Ann.REG_DATA, ['+/-%d g' % result]], stop_index, start_index) def handle_reg_0x32(self, data): self.data = data - self.putx([4, [str(data)]]) + self.putx([Ann.REG_DATA, [str(data)]]) def handle_reg_0x33(self, data): self.get_axis_value(data, 'X') @@ -346,31 +334,22 @@ class Decoder(srd.Decoder): Bit('', BitType.OTHER, {1: ['Trig-INT2', 'INT2'], 0: ['Trig-INT1', 'INT1'], })] bits_values = self.interpret_bits(data, bits) - start_index = 6 - stop_index = 7 + start_index, stop_index = 6, 7 fifo = self.get_decimal_number(bits_values, start_index, stop_index) - self.putbs([4, [fifo_modes[fifo]]], - self.reverse_bit_index(stop_index, WORD_SIZE), - self.reverse_bit_index(start_index, WORD_SIZE)) + self.putbs([Ann.REG_DATA, [fifo_modes[fifo]]], stop_index, start_index) - start_index = 0 - stop_index = 4 + start_index, stop_index = 0, 4 samples = self.get_decimal_number(bits_values, start_index, stop_index) - self.putbs([4, ['Samples: %d' % samples, '%d' % samples]], - self.reverse_bit_index(stop_index, WORD_SIZE), - self.reverse_bit_index(start_index, WORD_SIZE)) + self.putbs([Ann.REG_DATA, ['Samples: %d' % samples, '%d' % samples]], stop_index, start_index) def handle_reg_0x39(self, data): bits = [Bit('', BitType.OTHER, {1: ['Triggered', 'Trigg'], 0: ['Not triggered', 'Not trigg'],}), Bit('', BitType.UNUSED)] bits_values = self.interpret_bits(data, bits) - start_index = 0 - stop_index = 5 + start_index, stop_index = 0, 5 entries = self.get_decimal_number(bits_values, start_index, stop_index) - self.putbs([4, ['Entries: %d' % entries, '%d' % entries]], - self.reverse_bit_index(stop_index, WORD_SIZE), - self.reverse_bit_index(start_index, WORD_SIZE)) + self.putbs([Ann.REG_DATA, ['Entries: %d' % entries, '%d' % entries]], stop_index, start_index) def get_bit(self, channel): if (channel == Channel.MOSI and self.mosi is None) or \ @@ -397,11 +376,10 @@ class Decoder(srd.Decoder): if ptype == 'CS-CHANGE': cs_old, cs_new = data[1:] if cs_old is not None and cs_old == 1 and cs_new == 0: - self.ss = ss - self.es = es - self.state = 'ADDRESS-BYTE' + self.ss, self.es = ss, es + self.state = St.ADDRESS_BYTE else: - self.state = 'IDLE' + self.state = St.IDLE elif ptype == 'BITS': if data[1] is not None: @@ -412,19 +390,15 @@ class Decoder(srd.Decoder): if self.mosi is None and self.miso is None: return - if self.state == 'ADDRESS-BYTE': + if self.state == St.ADDRESS_BYTE: # OPERATION BIT op_bit = self.get_bit(Channel.MOSI) - if op_bit[0]: - self.put(op_bit[1], op_bit[2], self.out_ann, [0, operations[op_bit[0]]]) - self.operation = Operation.READ - else: - self.put(op_bit[1], op_bit[2], self.out_ann, [1, operations[op_bit[0]]]) - self.operation = Operation.WRITE - + self.put(op_bit[1], op_bit[2], self.out_ann, + [Ann.READ if op_bit[0] else Ann.WRITE, operations[op_bit[0]]]) + self.operation = Operation.READ if op_bit[0] else Operation.WRITE # MULTIPLE-BYTE BIT mb_bit = self.get_bit(Channel.MOSI) - self.put(mb_bit[1], mb_bit[2], self.out_ann, [2, number_bytes[mb_bit[0]]]) + self.put(mb_bit[1], mb_bit[2], self.out_ann, [Ann.MB, number_bytes[mb_bit[0]]]) # REGISTER 6-BIT ADDRESS self.address = 0 @@ -436,22 +410,17 @@ class Decoder(srd.Decoder): self.address <<= 1 self.address >>= 1 self.put(start_sample, addr_bit[2], self.out_ann, - [3, ['ADDRESS: 0x%02X' % self.address, 'ADDR: 0x%02X' + [Ann.REG_ADDRESS, ['ADDRESS: 0x%02X' % self.address, 'ADDR: 0x%02X' % self.address, '0x%02X' % self.address]]) self.ss = -1 - self.state = 'DATA' + self.state = St.DATA - elif self.state == 'DATA': - if self.operation == Operation.WRITE: - self.reg.extend(self.mosi) - elif self.operation == Operation.READ: - self.reg.extend(self.miso) + elif self.state == St.DATA: + self.reg.extend(self.mosi if self.operation == Operation.WRITE else self.miso) - self.mosi = [] - self.miso = [] + self.mosi, self.miso = [], [] if self.ss == -1: - self.ss = self.reg[0][1] - self.es = es + self.ss, self.es = self.reg[0][1], es self.samples_per_bit = self.reg[0][2] - self.ss if len(self.reg) < 8: @@ -472,11 +441,11 @@ class Decoder(srd.Decoder): self.start_index = self.ss if 0x1D > self.address >= 0x00: - self.put(self.ss, reg_bit[2], self.out_ann, [3, [str(self.address)]]) - self.put(self.ss, reg_bit[2], self.out_ann, [4, [str(reg_value)]]) + self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, [str(self.address)]]) + self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_DATA, [str(reg_value)]]) else: - self.put(self.ss, reg_bit[2], self.out_ann, [3, registers[self.address]]) - handle_reg = getattr(self, 'handle_reg_0x%02X' % self.address) + self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, registers[self.address]]) + handle_reg = getattr(self, 'handle_reg_0x%02x' % self.address) handle_reg(reg_value) self.reg = []