X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=Makefile.am;h=56d6230c9f8478467f46e874fa012216cd11df67;hb=edd28877cc74f9f0c063910d3cc24729db67f3f4;hp=78ae7c7d50d4c3be5d2a3bd3f25ed77d7bc889fd;hpb=0e1a7fe91a9132ad586337bdd29d93eff4344edd;p=libsigrok.git

diff --git a/Makefile.am b/Makefile.am
index 78ae7c7d..56d6230c 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -43,10 +43,10 @@ libsigrok_la_SOURCES = \
 
 # Input modules
 libsigrok_la_SOURCES += \
+	src/input/input.c \
 	src/input/binary.c \
 	src/input/chronovu_la8.c \
 	src/input/csv.c \
-	src/input/input.c \
 	src/input/vcd.c \
 	src/input/wav.c
 
@@ -264,6 +264,12 @@ libsigrok_la_SOURCES += \
 	src/hardware/openbench-logic-sniffer/protocol.c \
 	src/hardware/openbench-logic-sniffer/api.c
 endif
+if HW_PIPISTRELLO_OLS
+libsigrok_la_SOURCES += \
+	src/hardware/pipistrello-ols/protocol.h \
+	src/hardware/pipistrello-ols/protocol.c \
+	src/hardware/pipistrello-ols/api.c
+endif
 if HW_RIGOL_DS
 libsigrok_la_SOURCES += \
 	src/hardware/rigol-ds/protocol.h \
@@ -500,6 +506,7 @@ $(JDOC): bindings/swig/doc.py $(CPPXMLDOC)
 	$(AM_V_GEN)python $< java $(CPPXMLDOC) > $@
 
 $(JCXX): $(JSWG) $(JDOC) bindings/swig/classes.i $(library_include_HEADERS)
+	$(AM_V_at)make java-clean
 	$(AM_V_GEN)swig -c++ -java -package org.sigrok.core.classes \
 		-I$(srcdir)/include -I$(srcdir)/bindings/cxx/include -I$(srcdir) -I$(JCLS) -Ibindings/cxx/include -outdir $(JCLS) -o $@ $<