X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=src%2Fhardware%2Fasix-sigma%2Fprotocol.h;h=e780de4225523bb8c4f5bd513aacd72f7d865130;hb=156b6879e9ed8d4f1ee48e13b444822efc976420;hp=af4e5c103ebd29b24c208991eb5a624bfce76210;hpb=2c33b092553c4116151aeb59f129f2f0a598741e;p=libsigrok.git diff --git a/src/hardware/asix-sigma/protocol.h b/src/hardware/asix-sigma/protocol.h index af4e5c10..e780de42 100644 --- a/src/hardware/asix-sigma/protocol.h +++ b/src/hardware/asix-sigma/protocol.h @@ -4,6 +4,7 @@ * Copyright (C) 2010-2012 Håvard Espeland , * Copyright (C) 2010 Martin Stensgård * Copyright (C) 2010 Carl Henrik Lunde + * Copyright (C) 2020 Gerhard Sittig * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,7 +39,7 @@ * the implementation got fixed. Yet keep the code in place and allow * developers to turn on this switch during development. */ -#define ASIX_SIGMA_WITH_TRIGGER 0 +#define ASIX_SIGMA_WITH_TRIGGER 1 /* Experimental support for OMEGA (scan only, operation is ENOIMPL). */ #define ASIX_WITH_OMEGA 0 @@ -89,6 +90,12 @@ enum asix_device_type { * are available to applications and plugin features. Can libsigrok's * asix-sigma driver store configuration data there, to avoid expensive * operations (think: firmware re-load). + * + * Update: The documentation may be incorrect, or the FPGA netlist may + * be incomplete. Experiments show that registers beyond 0x0f can get + * accessed, USB communication passes, but data bytes are always 0xff. + * Are several firmware versions around, and the documentation does not + * match the one that ships with sigrok? */ enum sigma_write_register { @@ -102,6 +109,9 @@ enum sigma_write_register { WRITE_PIN_VIEW = 7, /* Unassigned register locations. */ WRITE_TEST = 15, + /* Reserved for plugin features. */ + REG_PLUGIN_START = 16, + REG_PLUGIN_STOP = 256, }; enum sigma_read_register { @@ -121,10 +131,47 @@ enum sigma_read_register { READ_PIN_VIEW = 13, /* Unassigned register location. */ READ_TEST = 15, + /* Reserved for plugin features. See above. */ +}; + +#define HI4(b) (((b) >> 4) & 0x0f) +#define LO4(b) (((b) >> 0) & 0x0f) + +#define BIT_MASK(l) ((1UL << (l)) - 1) + +#define CLKSEL_CLKSEL8 (1 << 0) +#define CLKSEL_PINMASK BIT_MASK(4) +#define CLKSEL_RISING (1 << 4) +#define CLKSEL_FALLING (1 << 5) + +#define TRGSEL_SELINC_MASK BIT_MASK(2) +#define TRGSEL_SELINC_SHIFT 0 +#define TRGSEL_SELRES_MASK BIT_MASK(2) +#define TRGSEL_SELRES_SHIFT 2 +#define TRGSEL_SELA_MASK BIT_MASK(2) +#define TRGSEL_SELA_SHIFT 4 +#define TRGSEL_SELB_MASK BIT_MASK(2) +#define TRGSEL_SELB_SHIFT 6 +#define TRGSEL_SELC_MASK BIT_MASK(2) +#define TRGSEL_SELC_SHIFT 8 +#define TRGSEL_SELPRESC_MASK BIT_MASK(4) +#define TRGSEL_SELPRESC_SHIFT 12 + +enum trgsel_selcode_t { + TRGSEL_SELCODE_LEVEL = 0, + TRGSEL_SELCODE_FALL = 1, + TRGSEL_SELCODE_RISE = 2, + TRGSEL_SELCODE_EVENT = 3, + TRGSEL_SELCODE_NEVER = 3, }; -#define LEDSEL0 6 -#define LEDSEL1 7 +#define TRGSEL2_PINS_MASK BIT_MASK(3) +#define TRGSEL2_PINPOL_RISE (1 << 3) +#define TRGSEL2_LUT_ADDR_MASK BIT_MASK(4) +#define TRGSEL2_LUT_WRITE (1 << 4) +#define TRGSEL2_RESET (1 << 5) +#define TRGSEL2_LEDSEL0 (1 << 6) +#define TRGSEL2_LEDSEL1 (1 << 7) /* WRITE_MODE register fields. */ #define WMR_SDRAMWRITEEN (1 << 0) @@ -146,6 +193,22 @@ enum sigma_read_register { #define RMR_POSTTRIGGERED (1 << 6) /* not used: bit position 7 */ +/* + * Trigger options. First and second write are similar, but _some_ + * positions change their meaning. + */ +#define TRGOPT_TRGIEN (1 << 7) +#define TRGOPT_TRGOEN (1 << 6) +#define TRGOPT_TRGOINEN (1 << 5) /* 1st write */ +#define TRGOPT_TRGINEG TRGOPT1_TRGOINEN /* 2nd write */ +#define TRGOPT_TRGOEVNTEN (1 << 4) /* 1st write */ +#define TRGOPT_TRGOPIN TRGOPT1_TRGOEVNTEN /* 2nd write */ +#define TRGOPT_TRGOOUTEN (1 << 3) /* 1st write */ +#define TRGOPT_TRGOLONG TRGOPT1_TRGOOUTEN /* 2nd write */ +#define TRGOPT_TRGOUTR_OUT (1 << 1) +#define TRGOPT_TRGOUTR_EN (1 << 0) +#define TRGOPT_CLEAR_MASK (TRGOPT_TRGOINEN | TRGOPT_TRGOEVNTEN | TRGOPT_TRGOOUTEN) + /* * Layout of the sample data DRAM, which will be downloaded to the PC: * @@ -189,60 +252,28 @@ enum sigma_read_register { struct sigma_dram_line { struct sigma_dram_cluster { - uint8_t timestamp_lo; - uint8_t timestamp_hi; - struct sigma_dram_event { - uint8_t sample_hi; - uint8_t sample_lo; - } samples[EVENTS_PER_CLUSTER]; + uint16_t timestamp; + uint16_t samples[EVENTS_PER_CLUSTER]; } cluster[CLUSTERS_PER_ROW]; }; -struct clockselect_50 { - uint8_t async; - uint8_t fraction; - uint16_t disabled_channels; -}; - /* The effect of all these are still a bit unclear. */ struct triggerinout { - uint8_t trgout_resistor_enable : 1; - uint8_t trgout_resistor_pullup : 1; - uint8_t reserved1 : 1; - uint8_t trgout_bytrigger : 1; - uint8_t trgout_byevent : 1; - uint8_t trgout_bytriggerin : 1; - uint8_t reserved2 : 2; - - /* Should be set same as the first two */ - uint8_t trgout_resistor_enable2 : 1; - uint8_t trgout_resistor_pullup2 : 1; - - uint8_t reserved3 : 1; - uint8_t trgout_long : 1; - uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */ - uint8_t trgin_negate : 1; - uint8_t trgout_enable : 1; - uint8_t trgin_enable : 1; + gboolean trgout_resistor_enable, trgout_resistor_pullup; + gboolean trgout_resistor_enable2, trgout_resistor_pullup2; + gboolean trgout_bytrigger, trgout_byevent, trgout_bytriggerin; + gboolean trgout_long, trgout_pin; /* 1ms pulse, 1k resistor */ + gboolean trgin_negate, trgout_enable, trgin_enable; }; struct triggerlut { - /* The actual LUTs. */ uint16_t m0d[4], m1d[4], m2d[4]; - uint16_t m3, m3s, m4; - - /* Parameters should be sent as a single register write. */ + uint16_t m3q, m3s, m4; struct { - uint8_t selc : 2; - uint8_t selpresc : 6; - - uint8_t selinc : 2; - uint8_t selres : 2; - uint8_t sela : 2; - uint8_t selb : 2; - - uint16_t cmpb; - uint16_t cmpa; + uint8_t selpresc; + uint8_t sela, selb, selc; + uint8_t selinc, selres; + uint16_t cmpa, cmpb; } params; }; @@ -284,6 +315,7 @@ enum triggerfunc { struct sigma_state { enum { SIGMA_UNINITIALIZED = 0, + SIGMA_CONFIG, SIGMA_IDLE, SIGMA_CAPTURE, SIGMA_STOPPING, @@ -293,6 +325,23 @@ struct sigma_state { uint16_t lastsample; }; +enum sigma_firmware_idx { + SIGMA_FW_NONE, + SIGMA_FW_50MHZ, + SIGMA_FW_100MHZ, + SIGMA_FW_200MHZ, + SIGMA_FW_SYNC, + SIGMA_FW_FREQ, +}; + +enum ext_clock_edge_t { + SIGMA_CLOCK_EDGE_RISING, + SIGMA_CLOCK_EDGE_FALLING, + SIGMA_CLOCK_EDGE_EITHER, +}; + +struct submit_buffer; + struct dev_context { struct { uint16_t vid, pid; @@ -300,34 +349,66 @@ struct dev_context { uint16_t prefix; enum asix_device_type type; } id; - struct ftdi_context ftdic; - uint64_t cur_samplerate; - uint64_t limit_msec; - uint64_t limit_samples; - uint64_t sent_samples; - uint64_t start_time; - int cur_firmware; - int num_channels; - int cur_channels; - int samples_per_event; + struct { + struct ftdi_context ctx; + gboolean is_open, must_close; + } ftdi; + struct { + uint64_t samplerate; + gboolean use_ext_clock; + size_t clock_pin; + enum ext_clock_edge_t clock_edge; + } clock; + struct { + /* + * User specified configuration values, in contrast to + * internal arrangement of acquisition, and submission + * to the session feed. + */ + struct sr_sw_limits config; + struct sr_sw_limits acquire; + struct sr_sw_limits submit; + } limit; + enum sigma_firmware_idx firmware_idx; + size_t num_channels; + size_t samples_per_event; uint64_t capture_ratio; struct sigma_trigger trigger; - int use_triggers; + gboolean use_triggers; struct sigma_state state; + struct submit_buffer *buffer; }; -extern SR_PRIV const uint64_t samplerates[]; -extern SR_PRIV const size_t samplerates_count; - -SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, - struct dev_context *devc); -SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc); -SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc); -SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, - uint64_t limit_samples); -SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate); +/* "Automatic" and forced USB connection open/close support. */ +SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi); +SR_PRIV int sigma_check_close(struct dev_context *devc); +SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi); +SR_PRIV int sigma_force_close(struct dev_context *devc); + +/* Save configuration across sessions, to reduce cost of continuation. */ +SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi); +SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi); + +/* Send register content (simple and complex) to the hardware. */ +SR_PRIV int sigma_write_register(struct dev_context *devc, + uint8_t reg, uint8_t *data, size_t len); +SR_PRIV int sigma_set_register(struct dev_context *devc, + uint8_t reg, uint8_t value); +SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, + struct triggerlut *lut); + +/* Samplerate constraints check, get/set/list helpers. */ +SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate); +SR_PRIV GVariant *sigma_get_samplerates_list(void); + +/* Preparation of data acquisition, spec conversion, hardware configuration. */ +SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi); +SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc); SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi); +SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, + struct triggerlut *lut); + +/* Callback to periodically drive acuisition progress. */ SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data); -SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc); #endif