X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=src%2Fhardware%2Fasix-sigma%2Fprotocol.h;h=388b44bc9f659e0b96838dce8f35fda368781357;hb=13262b48c181ae380e2029982197649cb6343b9f;hp=3621f157d3c2b5ba73c0329010af488fd017f550;hpb=9a0a606a8215aa7fd41bb72a3653dff7ef54505b;p=libsigrok.git

diff --git a/src/hardware/asix-sigma/protocol.h b/src/hardware/asix-sigma/protocol.h
index 3621f157..388b44bc 100644
--- a/src/hardware/asix-sigma/protocol.h
+++ b/src/hardware/asix-sigma/protocol.h
@@ -30,6 +30,14 @@
 #include <libsigrok/libsigrok.h>
 #include "libsigrok-internal.h"
 
+/*
+ * Triggers are not working in this implementation. Stop claiming
+ * support for the feature which effectively is not available, until
+ * the implementation got fixed. Yet keep the code in place and allow
+ * developers to turn on this switch during development.
+ */
+#define ASIX_SIGMA_WITH_TRIGGER	0
+
 #define LOG_PREFIX "asix-sigma"
 
 #define USB_VENDOR			0xa600
@@ -90,8 +98,51 @@ enum sigma_read_register {
 
 #define CHUNK_SIZE		1024
 
+/* WRITE_MODE register fields. */
+#define WMR_SDRAMWRITEEN	(1 << 0)
+#define WMR_SDRAMREADEN		(1 << 1)
+#define WMR_TRGRES		(1 << 2)
+#define WMR_TRGEN		(1 << 3)
+#define WMR_FORCESTOP		(1 << 4)
+#define WMR_TRGSW		(1 << 5)
+/* not used: bit position 6 */
+#define WMR_SDRAMINIT		(1 << 7)
+
+/* READ_MODE register fields. */
+#define RMR_SDRAMWRITEEN	(1 << 0)
+#define RMR_SDRAMREADEN		(1 << 1)
+/* not used: bit position 2 */
+#define RMR_TRGEN		(1 << 3)
+#define RMR_ROUND		(1 << 4)
+#define RMR_TRIGGERED		(1 << 5)
+#define RMR_POSTTRIGGERED	(1 << 6)
+/* not used: bit position 7 */
+
 /*
- * The entire ASIX Sigma DRAM is an array of struct sigma_dram_line[1024];
+ * Layout of the sample data DRAM, which will be downloaded to the PC:
+ *
+ * Sigma memory is organized in 32K rows. Each row contains 64 clusters.
+ * Each cluster contains a timestamp (16bit) and 7 samples (16bits each).
+ * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MB (256 Mbit).
+ *
+ * Sample data is represented in 16bit quantities. The first sample in
+ * the cluster corresponds to the cluster's timestamp. Each next sample
+ * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is
+ * one sample period, according to the samplerate). In the absence of
+ * pin level changes, no data is provided (RLE compression). A cluster
+ * is enforced for each 64K ticks of the timestamp, to reliably handle
+ * rollover and determination of the next timestamp of the next cluster.
+ *
+ * For samplerates of 100MHz, there is one 16 bit entity for each 20ns
+ * period (50MHz rate). The 16 bit memory contains 2 samples of up to
+ * 8 channels. Bits of multiple samples are interleaved. For samplerates
+ * of 200MHz one 16bit entity contains 4 samples of up to 4 channels,
+ * each 5ns apart.
+ *
+ * Memory addresses (sample count, trigger position) are kept in 24bit
+ * entities. The upper 15 bit refer to the "row", the lower 9 bit refer
+ * to the "event" within the row. Because there is one timestamp for
+ * seven samples each, one memory row can hold up to 64x7 == 448 samples.
  */
 
 /* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */
@@ -208,9 +259,9 @@ struct sigma_state {
 struct dev_context {
 	struct ftdi_context ftdic;
 	uint64_t cur_samplerate;
-	uint64_t period_ps;
 	uint64_t limit_msec;
 	uint64_t limit_samples;
+	uint64_t sent_samples;
 	struct timeval start_tv;
 	int cur_firmware;
 	int num_channels;