X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=src%2Fhardware%2Fasix-sigma%2Fprotocol.c;h=b23b26ff832cca1cb4d0d8aa1d938c1631512bf2;hb=4154a516de818ace3aabfe5e44cf4c81986074e7;hp=8f07a0d8117bfaf756d0e1911ad4479f741f148b;hpb=3ba56876b4a5469b0c39a6f162f517ce8610b9e4;p=libsigrok.git diff --git a/src/hardware/asix-sigma/protocol.c b/src/hardware/asix-sigma/protocol.c index 8f07a0d8..b23b26ff 100644 --- a/src/hardware/asix-sigma/protocol.c +++ b/src/hardware/asix-sigma/protocol.c @@ -32,8 +32,6 @@ #define USB_VENDOR_NAME "ASIX" #define USB_MODEL_NAME "SIGMA" -SR_PRIV struct sr_dev_driver asix_sigma_driver_info; - /* * The ASIX Sigma supports arbitrary integer frequency divider in * the 50MHz mode. The divider is in range 1...256 , allowing for @@ -53,7 +51,7 @@ SR_PRIV const uint64_t samplerates[] = { SR_MHZ(200), /* Special FW needed */ }; -SR_PRIV const int SAMPLERATES_COUNT = ARRAY_SIZE(samplerates); +SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates); static const char sigma_firmware_files[][24] = { /* 50 MHz, supports 8 bit fractions */ @@ -116,7 +114,7 @@ SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, buf[idx++] = REG_ADDR_LOW | (reg & 0xf); buf[idx++] = REG_ADDR_HIGH | (reg >> 4); - for (i = 0; i < len; ++i) { + for (i = 0; i < len; i++) { buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); } @@ -203,7 +201,7 @@ static int sigma_read_dram(uint16_t startchunk, size_t numchunks, buf[idx++] = REG_DRAM_BLOCK; buf[idx++] = REG_DRAM_WAIT_ACK; - for (i = 0; i < numchunks; ++i) { + for (i = 0; i < numchunks; i++) { /* Alternate bit to copy from DRAM to cache. */ if (i != (numchunks - 1)) buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); @@ -227,7 +225,7 @@ SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context * uint16_t bit; /* Transpose the table and send to Sigma. */ - for (i = 0; i < 16; ++i) { + for (i = 0; i < 16; i++) { bit = 1 << i; tmp[0] = tmp[1] = 0; @@ -390,12 +388,13 @@ static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, int bit, v; int ret = SR_OK; + /* Retrieve the on-disk firmware file content. */ firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, name, &file_size, 256 * 1024); if (!firmware) return SR_ERR; - /* Weird magic transformation below, I have no idea what it does. */ + /* Unscramble the file content (XOR with "random" sequence). */ imm = 0x3f6df2ab; for (i = 0; i < file_size; i++) { imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); @@ -403,13 +402,20 @@ static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, } /* - * Now that the firmware is "transformed", we will transcribe the - * firmware blob into a sequence of toggles of the Dx wires. This - * sequence will be fed directly into the Sigma, which must be in - * the FPGA bitbang programming mode. + * Generate a sequence of bitbang samples. With two samples per + * FPGA configuration bit, providing the level for the DIN signal + * as well as two edges for CCLK. See Xilinx UG332 for details + * ("slave serial" mode). + * + * Note that CCLK is inverted in hardware. That's why the + * respective bit is first set and then cleared in the bitbang + * sample sets. So that the DIN level will be stable when the + * data gets sampled at the rising CCLK edge, and the signals' + * setup time constraint will be met. + * + * The caller will put the FPGA into download mode, will send + * the bitbang samples, and release the allocated memory. */ - - /* Each bit of firmware is transcribed as two toggles of Dx wires. */ bb_size = file_size * 8 * 2; bb_stream = (uint8_t *)g_try_malloc(bb_size); if (!bb_stream) { @@ -417,7 +423,6 @@ static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, ret = SR_ERR_MALLOC; goto exit; } - bbs = bb_stream; for (i = 0; i < file_size; i++) { for (bit = 7; bit >= 0; bit--) { @@ -518,18 +523,18 @@ SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t sampler { struct dev_context *devc; struct drv_context *drvc; - unsigned int i; + size_t i; int ret; devc = sdi->priv; drvc = sdi->driver->context; ret = SR_OK; - for (i = 0; i < ARRAY_SIZE(samplerates); i++) { + for (i = 0; i < samplerates_count; i++) { if (samplerates[i] == samplerate) break; } - if (samplerates[i] == 0) + if (i >= samplerates_count || samplerates[i] == 0) return SR_ERR_SAMPLERATE; if (samplerate <= SR_MHZ(50)) { @@ -601,7 +606,7 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) return SR_ERR; } - ++trigger_set; + trigger_set++; } else { /* Simple trigger support (event). */ if (match->match == SR_TRIGGER_ONE) { @@ -614,11 +619,11 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) } else if (match->match == SR_TRIGGER_FALLING) { devc->trigger.fallingmask |= channelbit; - ++trigger_set; + trigger_set++; } else if (match->match == SR_TRIGGER_RISING) { devc->trigger.risingmask |= channelbit; - ++trigger_set; + trigger_set++; } /* @@ -646,7 +651,7 @@ static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, int i; uint16_t sample = 0; - for (i = 0; i < 8; ++i) { + for (i = 0; i < 8; i++) { if (i > 0) last_sample = sample; sample = samples[2 * i] | (samples[2 * i + 1] << 8); @@ -837,7 +842,6 @@ static int download_capture(struct sr_dev_inst *sdi) struct sigma_dram_line *dram_line; int bufsz; uint32_t stoppos, triggerpos; - struct sr_datafeed_packet packet; uint8_t modestatus; uint32_t i; @@ -909,11 +913,9 @@ static int download_capture(struct sr_dev_inst *sdi) dl_lines_done += dl_lines_curr; } - /* All done. */ - packet.type = SR_DF_END; - sr_session_send(sdi, &packet); + std_session_send_df_end(sdi); - sdi->driver->dev_acquisition_stop(sdi, sdi); + sdi->driver->dev_acquisition_stop(sdi); g_free(dram_line); @@ -978,20 +980,19 @@ static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) int i, j, k, bit; /* For each quad channel. */ - for (i = 0; i < 4; ++i) { + for (i = 0; i < 4; i++) { entry[i] = 0xffff; /* For each bit in LUT. */ - for (j = 0; j < 16; ++j) + for (j = 0; j < 16; j++) /* For each channel in quad. */ - for (k = 0; k < 4; ++k) { + for (k = 0; k < 4; k++) { bit = 1 << (i * 4 + k); /* Set bit in entry */ - if ((mask & bit) && - ((!(value & bit)) != - (!(j & (1 << k))))) + if ((mask & bit) && ((!(value & bit)) != + (!(j & (1 << k))))) entry[i] &= ~(1 << j); } } @@ -1044,17 +1045,17 @@ static void add_trigger_function(enum triggerop oper, enum triggerfunc func, /* Transpose if neg is set. */ if (neg) { - for (i = 0; i < 2; ++i) { - for (j = 0; j < 2; ++j) { + for (i = 0; i < 2; i++) { + for (j = 0; j < 2; j++) { tmp = x[i][j]; - x[i][j] = x[1-i][1-j]; - x[1-i][1-j] = tmp; + x[i][j] = x[1 - i][1 - j]; + x[1 - i][1 - j] = tmp; } } } /* Update mask with function. */ - for (i = 0; i < 16; ++i) { + for (i = 0; i < 16; i++) { a = (i >> (2 * index + 0)) & 1; b = (i >> (2 * index + 1)) & 1; @@ -1099,7 +1100,7 @@ SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context lut->m2d); /* Rise/fall trigger support. */ - for (i = 0, j = 0; i < 16; ++i) { + for (i = 0, j = 0; i < 16; i++) { if (devc->trigger.risingmask & (1 << i) || devc->trigger.fallingmask & (1 << i)) masks[j++] = 1 << i;