X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=decoders%2Fusb_signalling%2Fpd.py;h=8225ae7cb9e4bdb7191ca8b61c76c179bc76ae71;hb=9821622af021360a92334d1a6b465c8e3aab90b6;hp=6233c3eb6462967f2d6bf6a03b512f7919ff5c8f;hpb=519092e31aa4f2288dd82d43719d5a88d4e465b9;p=libsigrokdecode.git

diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index 6233c3e..8225ae7 100644
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -69,10 +69,22 @@ symbols = {
         (0, 1): 'LS_J',
         (1, 1): 'SE1',
     },
+# After a PREamble PID, the bus segment between Host and Hub uses LS signalling
+# rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For both upstream and
+# downstream low-speed data, the hub is responsible for inverting the polarity of
+# the data before transmitting to/from a low-speed port."
+    'low-speed-rp': {
+        # (<dp>, <dm>): <symbol/state>
+        (0, 0): 'SE0',
+        (1, 0): 'J',
+        (0, 1): 'K',
+        (1, 1): 'SE1',
+    },
 }
 
 bitrates = {
     'low-speed': 1500000,   # 1.5Mb/s (+/- 1.5%)
+    'low-speed-rp': 1500000,   # 1.5Mb/s (+/- 1.5%)
     'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
     'automatic': None
 }
@@ -227,7 +239,7 @@ class Decoder(srd.Decoder):
             # Got an EOP.
             self.putpm(['EOP', None])
             self.putm([5, ['EOP', 'E']])
-            self.state = 'IDLE'
+            self.state = 'WAIT IDLE'
         else:
             self.putpm(['ERR', None])
             self.putm([8, ['EOP Error', 'EErr', 'E']])
@@ -272,6 +284,7 @@ class Decoder(srd.Decoder):
         elif sym == 'LS_J':
             self.signalling = 'low-speed'
             self.update_bitrate()
+        self.oldsym = 'J'
         self.state = 'IDLE'
 
     def decode(self, ss, es, data):
@@ -302,8 +315,9 @@ class Decoder(srd.Decoder):
                     self.get_bit(sym)
                 elif self.state == 'GET EOP':
                     self.get_eop(sym)
+                self.oldpins = pins
             elif self.state == 'WAIT IDLE':
-                if self.oldpins == pins:
+                if tuple(pins) == (0, 0):
                     continue
                 if self.samplenum - self.samplenum_lastedge > 1:
                     sym = symbols[self.options['signalling']][tuple(pins)]