X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=decoders%2Fspi%2Fpd.py;h=bb486c8fddc301fc1e50f5c21458469595ac0eb3;hb=191ec8c5b7b6bb6b348a2c43b851923181fd68d8;hp=10857866f4cad8ebdc41fe58600cdb688b8d6420;hpb=24c74fd30fb161837c5f8b01baf3c0fe2dfa4ed5;p=libsigrokdecode.git diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index 1085786..bb486c8 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -1,8 +1,8 @@ ## -## This file is part of the sigrok project. +## This file is part of the libsigrokdecode project. ## ## Copyright (C) 2011 Gareth McMullin -## Copyright (C) 2012 Uwe Hermann +## Copyright (C) 2012-2013 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -33,9 +33,6 @@ spi_mode = { (1, 1): 3, # Mode 3 } -# Annotation formats -ANN_HEX = 0 - class Decoder(srd.Decoder): api_version = 1 id = 'spi' @@ -60,9 +57,13 @@ class Decoder(srd.Decoder): 'cpha': ['Clock phase', 0], 'bitorder': ['Bit order within the SPI data', 'msb-first'], 'wordsize': ['Word size of SPI data', 8], # 1-64? + 'format': ['Data format', 'hex'], } annotations = [ - ['Hex', 'SPI data bytes in hex format'], + ['MISO/MOSI data', 'MISO/MOSI SPI data'], + ['MISO data', 'MISO SPI data'], + ['MOSI data', 'MOSI SPI data'], + ['Warnings', 'Human-readable warnings'], ] def __init__(self): @@ -71,10 +72,12 @@ class Decoder(srd.Decoder): self.mosidata = 0 self.misodata = 0 self.bytesreceived = 0 + self.startsample = -1 self.samplenum = -1 self.cs_was_deasserted_during_data_word = 0 self.oldcs = -1 self.oldpins = None + self.state = 'IDLE' def start(self, metadata): self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') @@ -83,84 +86,96 @@ class Decoder(srd.Decoder): def report(self): return 'SPI: %d bytes received' % self.bytesreceived - def decode(self, ss, es, data): - # TODO: Either MISO or MOSI could be optional. CS# is optional. - for (self.samplenum, pins) in data: + def putpw(self, data): + self.put(self.startsample, self.samplenum, self.out_proto, data) - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins, (miso, mosi, sck, cs) = pins, pins + def putw(self, data): + self.put(self.startsample, self.samplenum, self.out_ann, data) - if self.oldcs != cs: - # Send all CS# pin value changes. - self.put(self.samplenum, self.samplenum, self.out_proto, - ['CS-CHANGE', self.oldcs, cs]) - self.put(self.samplenum, self.samplenum, self.out_ann, - [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]]) - self.oldcs = cs + def handle_bit(self, miso, mosi, sck, cs): + # If this is the first bit, save its sample number. + if self.bitcount == 0: + self.startsample = self.samplenum + active_low = (self.options['cs_polarity'] == 'active-low') + deasserted = cs if active_low else not cs + if deasserted: + self.cs_was_deasserted_during_data_word = 1 - # Ignore sample if the clock pin hasn't changed. - if sck == self.oldsck: - continue + ws = self.options['wordsize'] - self.oldsck = sck - - # Sample data on rising/falling clock edge (depends on mode). - mode = spi_mode[self.options['cpol'], self.options['cpha']] - if mode == 0 and sck == 0: # Sample on rising clock edge - continue - elif mode == 1 and sck == 1: # Sample on falling clock edge - continue - elif mode == 2 and sck == 1: # Sample on falling clock edge - continue - elif mode == 3 and sck == 0: # Sample on rising clock edge - continue - - # If this is the first bit, save its sample number. - if self.bitcount == 0: - self.start_sample = self.samplenum - active_low = (self.options['cs_polarity'] == 'active-low') - deasserted = cs if active_low else not cs - if deasserted: - self.cs_was_deasserted_during_data_word = 1 - - ws = self.options['wordsize'] - - # Receive MOSI bit into our shift register. - if self.options['bitorder'] == 'msb-first': - self.mosidata |= mosi << (ws - 1 - self.bitcount) - else: - self.mosidata |= mosi << self.bitcount + # Receive MOSI bit into our shift register. + if self.options['bitorder'] == 'msb-first': + self.mosidata |= mosi << (ws - 1 - self.bitcount) + else: + self.mosidata |= mosi << self.bitcount - # Receive MISO bit into our shift register. - if self.options['bitorder'] == 'msb-first': - self.misodata |= miso << (ws - 1 - self.bitcount) - else: - self.misodata |= miso << self.bitcount + # Receive MISO bit into our shift register. + if self.options['bitorder'] == 'msb-first': + self.misodata |= miso << (ws - 1 - self.bitcount) + else: + self.misodata |= miso << self.bitcount - self.bitcount += 1 + self.bitcount += 1 - # Continue to receive if not enough bits were received, yet. - if self.bitcount != ws: - continue + # Continue to receive if not enough bits were received, yet. + if self.bitcount != ws: + return - self.put(self.start_sample, self.samplenum, self.out_proto, - ['DATA', self.mosidata, self.misodata]) - self.put(self.start_sample, self.samplenum, self.out_ann, - [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, - self.misodata)]]) + self.putpw(['DATA', self.mosidata, self.misodata]) + self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]]) + self.putw([1, ['%02X' % self.misodata]]) + self.putw([2, ['%02X' % self.mosidata]]) - if self.cs_was_deasserted_during_data_word: - self.put(self.start_sample, self.samplenum, self.out_ann, - [ANN_HEX, ['WARNING: CS# was deasserted during this ' - 'SPI data byte!']]) + if self.cs_was_deasserted_during_data_word: + self.putw([3, ['CS# was deasserted during this data word!']]) + + # Reset decoder state. + self.mosidata = 0 + self.misodata = 0 + self.bitcount = 0 - # Reset decoder state. - self.mosidata = 0 - self.misodata = 0 - self.bitcount = 0 + # Keep stats for summary. + self.bytesreceived += 1 - # Keep stats for summary. - self.bytesreceived += 1 + def find_clk_edge(self, miso, mosi, sck, cs): + if self.oldcs != cs: + # Send all CS# pin value changes. + self.put(self.samplenum, self.samplenum, self.out_proto, + ['CS-CHANGE', self.oldcs, cs]) + self.oldcs = cs + + # Ignore sample if the clock pin hasn't changed. + if sck == self.oldsck: + return + + self.oldsck = sck + + # Sample data on rising/falling clock edge (depends on mode). + mode = spi_mode[self.options['cpol'], self.options['cpha']] + if mode == 0 and sck == 0: # Sample on rising clock edge + return + elif mode == 1 and sck == 1: # Sample on falling clock edge + return + elif mode == 2 and sck == 1: # Sample on falling clock edge + return + elif mode == 3 and sck == 0: # Sample on rising clock edge + return + + # Found the correct clock edge, now get the SPI bit(s). + self.handle_bit(miso, mosi, sck, cs) + + def decode(self, ss, es, data): + # TODO: Either MISO or MOSI could be optional. CS# is optional. + for (self.samplenum, pins) in data: + + # Ignore identical samples early on (for performance reasons). + if self.oldpins == pins: + continue + self.oldpins, (miso, mosi, sck, cs) = pins, pins + + # State machine. + if self.state == 'IDLE': + self.find_clk_edge(miso, mosi, sck, cs) + else: + raise Exception('Invalid state: %s' % self.state)