X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;ds=sidebyside;f=decoders%2Fi2c%2Fpd.py;h=d9061f5d12d1848f5d04b839769947b0226d1d7d;hb=647aba6af7745c14961674c5feebf83fd18303a3;hp=e70c27de27b301ffcc52d12bf800f141263d3eb1;hpb=8accc30bf5d98aa958af839511d57e0e1ddefe94;p=libsigrokdecode.git diff --git a/decoders/i2c/pd.py b/decoders/i2c/pd.py index e70c27d..d9061f5 100644 --- a/decoders/i2c/pd.py +++ b/decoders/i2c/pd.py @@ -21,6 +21,7 @@ # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). # TODO: Implement support for detecting various bus errors. +from common.srdhelper import bitpack_msb import sigrokdecode as srd ''' @@ -70,6 +71,7 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['i2c'] + tags = ['Embedded/industrial'] channels = ( {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, @@ -89,11 +91,11 @@ class Decoder(srd.Decoder): ('address-write', 'Address write'), ('data-read', 'Data read'), ('data-write', 'Data write'), - ('warnings', 'Human-readable warnings'), + ('warning', 'Warning'), ) annotation_rows = ( ('bits', 'Bits', (5,)), - ('addr-data', 'Address/Data', (0, 1, 2, 3, 4, 6, 7, 8, 9)), + ('addr-data', 'Address/data', (0, 1, 2, 3, 4, 6, 7, 8, 9)), ('warnings', 'Warnings', (10,)), ) binary = ( @@ -109,14 +111,13 @@ class Decoder(srd.Decoder): def reset(self): self.samplerate = None self.ss = self.es = self.ss_byte = -1 - self.bitcount = 0 - self.databyte = 0 - self.wr = -1 - self.is_repeat_start = 0 + self.is_write = None + self.rem_addr_bytes = None + self.is_repeat_start = False self.state = 'FIND START' self.pdu_start = None self.pdu_bits = 0 - self.bits = [] + self.data_bits = [] def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: @@ -142,76 +143,99 @@ class Decoder(srd.Decoder): self.ss, self.es = self.samplenum, self.samplenum self.pdu_start = self.samplenum self.pdu_bits = 0 - cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START' + cmd = 'START REPEAT' if self.is_repeat_start else 'START' self.putp([cmd, None]) self.putx([proto[cmd][0], proto[cmd][1:]]) self.state = 'FIND ADDRESS' - self.bitcount = self.databyte = 0 - self.is_repeat_start = 1 - self.wr = -1 - self.bits = [] + self.is_repeat_start = True + self.is_write = None + self.rem_addr_bytes = None + self.data_bits.clear() # Gather 8 bits of data plus the ACK/NACK bit. def handle_address_or_data(self, pins): scl, sda = pins self.pdu_bits += 1 - # Address and data are transmitted MSB-first. - self.databyte <<= 1 - self.databyte |= sda - - # Remember the start of the first data/address bit. - if self.bitcount == 0: + # Accumulate a byte's bits, including its start position. + # Accumulate individual bits and their start/end sample numbers + # as we see them. Get the start sample number at the time when + # the bit value gets sampled. Assume the start of the next bit + # as the end sample number of the previous bit. Guess the last + # bit's end sample number from the second last bit's width. + # (gsi: Shouldn't falling SCL be the end of the bit value?) + # Keep the bits in receive order (MSB first) during accumulation. + if not self.data_bits: self.ss_byte = self.samplenum - - # Store individual bits and their start/end samplenumbers. - # In the list, index 0 represents the LSB (I²C transmits MSB-first). - self.bits.insert(0, [sda, self.samplenum, self.samplenum]) - if self.bitcount > 0: - self.bits[1][2] = self.samplenum - if self.bitcount == 7: - self.bitwidth = self.bits[1][2] - self.bits[2][2] - self.bits[0][2] += self.bitwidth - - # Return if we haven't collected all 8 + 1 bits, yet. - if self.bitcount < 7: - self.bitcount += 1 + if self.data_bits: + self.data_bits[-1][2] = self.samplenum + self.data_bits.append([sda, self.samplenum, self.samplenum]) + if len(self.data_bits) < 8: return + self.bitwidth = self.data_bits[-2][2] - self.data_bits[-3][2] + self.data_bits[-1][2] += self.bitwidth - d = self.databyte + # Get the byte value. Address and data are transmitted MSB-first. + d = bitpack_msb(self.data_bits, 0) if self.state == 'FIND ADDRESS': - # The READ/WRITE bit is only in address bytes, not data bytes. - self.wr = 0 if (self.databyte & 1) else 1 - if self.options['address_format'] == 'shifted': - d = d >> 1 + # The READ/WRITE bit is only in the first address byte, not + # in data bytes. Address bit pattern 0b1111_0xxx means that + # this is a 10bit slave address, another byte follows. Get + # the R/W direction and the address bytes count from the + # first byte in the I2C transfer. + addr_byte = d + if self.rem_addr_bytes is None: + if (addr_byte & 0xf8) == 0xf0: + self.rem_addr_bytes = 2 + self.slave_addr_7 = None + self.slave_addr_10 = addr_byte & 0x06 + self.slave_addr_10 <<= 7 + else: + self.rem_addr_bytes = 1 + self.slave_addr_7 = addr_byte >> 1 + self.slave_addr_10 = None + is_seven = self.slave_addr_7 is not None + if self.is_write is None: + read_bit = bool(addr_byte & 1) + shift_seven = self.options['address_format'] == 'shifted' + if is_seven and shift_seven: + d = d >> 1 + self.is_write = False if read_bit else True + else: + self.slave_addr_10 |= addr_byte bin_class = -1 - if self.state == 'FIND ADDRESS' and self.wr == 1: + if self.state == 'FIND ADDRESS' and self.is_write: cmd = 'ADDRESS WRITE' bin_class = 1 - elif self.state == 'FIND ADDRESS' and self.wr == 0: + elif self.state == 'FIND ADDRESS' and not self.is_write: cmd = 'ADDRESS READ' bin_class = 0 - elif self.state == 'FIND DATA' and self.wr == 1: + elif self.state == 'FIND DATA' and self.is_write: cmd = 'DATA WRITE' bin_class = 3 - elif self.state == 'FIND DATA' and self.wr == 0: + elif self.state == 'FIND DATA' and not self.is_write: cmd = 'DATA READ' bin_class = 2 self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth - self.putp(['BITS', self.bits]) + # Reverse the list of bits to LSB first order before emitting + # annotations and passing bits to upper layers. This may be + # unexpected because the protocol is MSB first, but it keeps + # backwards compatibility. + self.data_bits.reverse() + self.putp(['BITS', self.data_bits]) self.putp([cmd, d]) self.putb([bin_class, bytes([d])]) - for bit in self.bits: + for bit in self.data_bits: self.put(bit[1], bit[2], self.out_ann, [5, ['%d' % bit[0]]]) - if cmd.startswith('ADDRESS'): + if cmd.startswith('ADDRESS') and is_seven: self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth - w = ['Write', 'Wr', 'W'] if self.wr else ['Read', 'Rd', 'R'] + w = ['Write', 'Wr', 'W'] if self.is_write else ['Read', 'Rd', 'R'] self.putx([proto[cmd][0], w]) self.ss, self.es = self.ss_byte, self.samplenum @@ -219,8 +243,7 @@ class Decoder(srd.Decoder): '%s: %02X' % (proto[cmd][2], d), '%02X' % d]]) # Done with this packet. - self.bitcount = self.databyte = 0 - self.bits = [] + self.data_bits.clear() self.state = 'FIND ACK' def get_ack(self, pins): @@ -229,9 +252,16 @@ class Decoder(srd.Decoder): cmd = 'NACK' if (sda == 1) else 'ACK' self.putp([cmd, None]) self.putx([proto[cmd][0], proto[cmd][1:]]) - # There could be multiple data bytes in a row, so either find - # another data byte or a STOP condition next. - self.state = 'FIND DATA' + # Slave addresses can span one or two bytes, before data bytes + # follow. There can be an arbitrary number of data bytes. Stick + # with getting more address bytes if applicable, or enter or + # remain in the data phase of the transfer otherwise. + if self.rem_addr_bytes: + self.rem_addr_bytes -= 1 + if self.rem_addr_bytes: + self.state = 'FIND ADDRESS' + else: + self.state = 'FIND DATA' def handle_stop(self, pins): # Meta bitrate @@ -245,9 +275,9 @@ class Decoder(srd.Decoder): self.putp([cmd, None]) self.putx([proto[cmd][0], proto[cmd][1:]]) self.state = 'FIND START' - self.is_repeat_start = 0 - self.wr = -1 - self.bits = [] + self.is_repeat_start = False + self.is_write = None + self.data_bits.clear() def decode(self): while True: